Prosecution Insights
Last updated: July 17, 2026
Application No. 18/962,199

PART INVARIANT PEAK POWER MANAGEMENT

Non-Final OA §102
Filed
Nov 27, 2024
Examiner
JOHNSON, TERRELL S
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
NVIDIA Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
425 granted / 491 resolved
+31.6% vs TC avg
Moderate +11% lift
Without
With
+10.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
14 currently pending
Career history
501
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
58.8%
+18.8% vs TC avg
§102
26.3%
-13.7% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 491 resolved cases

Office Action

§102
DETAILED ACTION Status of Claims Claims 1 – 20 are pending. Claims 1, 11, and 18 are independent. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 4, 7 – 10, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Govindaraju et al. (US Patent Application Publication No. 2015/0317764 , hereinafter “Govindaraju“). As per claim 1, Govindaraju teaches one or more processors comprising: one or more circuits to [fig. 1, fig. 6, 0010, 0011, 0051]: receive a plurality of instructions for a graphics processing device, the plurality of instructions corresponding to a respective plurality of power consumption values [fig. 1, 0011, 0015: a graphics translator 108 (sometimes referred to as graphics driver) running on the OS kernel 136 receives instructions from the media player running at the application level 134 to stream a video file. The example graphics translator 108 may then instruct an example graphics engine 122 regarding what data to process, when to process that data, how to process that data, etc. In the illustrated example of FIG. 1, the hardware layer 138 includes the hardware components that perform data processing. For example, the graphics engine 122 may take data corresponding to the instructions from the graphics translator 108 and perform video transcoding.]; determine that the respective plurality of power consumption values cause a threshold to be exceeded during a time period [Abstract, Fig.4, (415, 420), 0019: the sensor monitor 110 may gather current power information from one or more power sensors coupled to the CPU 112 and determine the instant power consumed by the CPU 112 based on the gathered information. In some examples, the sensor monitor 110 outputs an indication corresponding to the power consumed, such as a range of power consumed over one or more periods of time; 0028- 0030: ]; and generate a control signal to control a clock signal for the graphics processing device responsive to determining that the respective plurality of power consumption values cause the threshold to be exceeded [Abstract, fig.1, 0012, 0023, 0029]. As per claim 2, Govindaraju teaches the one or more processors of claim 1, wherein the one or more circuits are to: determine an average or aggregated value of the respective plurality of power consumption values according to a sliding window size; and determine that the average or aggregated value exceeds the threshold during the time period [0029, 0030, claim 7: calculating an average power consumed by the graphics engine of the first node during the correction period; and setting the graphics engine of the first node to the second graphics state when the average power consumed by the graphics engine of the first node during the correction period satisfies the corresponding node power threshold value]. As per claim 4, Govindaraju teaches the one or more processors of claim 1, wherein the one or more circuits are to: receive a signal to modify the threshold; and update the threshold according to the signal [fig. 1, 0016, 0017, 0026]. As per claim 7, Govindaraju teaches the one or more processors of claim 1, wherein the one or more circuits are to: generate the control signal according to a table of stepping values; and control a frequency of the clock signal according to the control signal [fig.1, 0023: data structure 118 specifies a frequency at which the graphics engine 122 operates as a percentage of a maximum frequency]. As per claim 8, Govindaraju teaches the one or more processors of claim 1, wherein the one or more circuits are to: receive a second plurality of instructions corresponding to a respective second plurality of power consumption values; determine that the respective second plurality of power consumption values do not cause the threshold to be exceeded during a second time period; and generate a second control signal for the graphics processing device to increase a frequency of the clock signal [0027: when power consumption is less that the power budget 202, the power controller 116 may execute actions to increase the workload performed by the graphics engine]. As per claim 9, Govindaraju teaches the one or more processors of claim 1, wherein the graphics processing device comprises a graphics processing cluster (GPC) [0022, 0025: execution units 124, 126, and 128]. As per claim 10, Govindaraju teaches the one or more processors of claim 1, wherein the one or more processors are comprised in at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations; a system for performing digital twin operations; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; a system for performing deep learning operations; a system implemented using an edge device; a system implemented using a robot; a system for performing conversational AI operations; a system for performing generative AI operations using a large language model (LLM); a system for performing generative AI operations using a vision language model (VLM); a system for performing generative AI operations using a multimodal language model; a system for generating synthetic data; a system incorporating one or more virtual machines (VMs); a system implemented at least partially in a data center; or a system implemented at least partially using cloud computing resources [data center, fig.3, 0009, 0012, 0034]. As per claim 18, Govindaraju teaches a method, comprising: receiving a plurality of instructions for a graphics processing device, the plurality of instructions corresponding to a respective plurality of power consumption values [fig. 1, 0011, 0015: a graphics translator 108 (sometimes referred to as graphics driver) running on the OS kernel 136 receives instructions from the media player running at the application level 134 to stream a video file. The example graphics translator 108 may then instruct an example graphics engine 122 regarding what data to process, when to process that data, how to process that data, etc. In the illustrated example of FIG. 1, the hardware layer 138 includes the hardware components that perform data processing. For example, the graphics engine 122 may take data corresponding to the instructions from the graphics translator 108 and perform video transcoding.];; determining that the respective plurality of power consumption values cause a threshold to be exceeded during a time period [Abstract, Fig.4, (415, 420), 0019: the sensor monitor 110 may gather current power information from one or more power sensors coupled to the CPU 112 and determine the instant power consumed by the CPU 112 based on the gathered information. In some examples, the sensor monitor 110 outputs an indication corresponding to the power consumed, such as a range of power consumed over one or more periods of time; 0028- 0030: ]; and generating a control signal to control a clock signal for the graphics processing device responsive to determining that the respective plurality of power consumption values cause the threshold to be exceeded [0011, 0029, 0030]. As per claim 19, Govindaraju teaches the method of claim 18, further comprising: determining an average or aggregated value of the respective plurality of power consumption values according to a sliding window size; and determining that the average or aggregated value exceeds the threshold during the time period [0029, 0030, claim 7: calculating an average power consumed by the graphics engine of the first node during the correction period; and setting the graphics engine of the first node to the second graphics state when the average power consumed by the graphics engine of the first node during the correction period satisfies the corresponding node power threshold value]. Allowable Subject Matter Claims 11 – 17 are allowed. Claims 3, 5, 6, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Turullols; Sebastian et al. (US Patent No. 11,709,522 B1) “Power And Temperature Driven Clock Throttling” is cited to teach techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds. Cha; Hungse et al. (US Patent No. 8,060,765) “Power Estimation Based On Block Activity” is cited to teach a power monitor for electronic devices, such as computer chips, is used to estimate the power consumption and to compare the estimated power consumption against the power budget. The estimated power consumption is based on activity signals from various functional blocks of the computer chip. The activity signals that are monitored correlate accurately to the total number of flip-flops that are active at a given time. If the estimated power consumption exceeds the power budget, the speed of the clock signals supplied to the computer chip is reduced. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
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Prosecution Timeline

Nov 27, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+10.6%)
2y 8m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 491 resolved cases by this examiner. Grant probability derived from career allowance rate.

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