Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to the amendment filed 08/31/2026. Claims 1-22 remain pending in the application. Applicant failed to address the specification objection in their reply, therefore, the objection is maintained. Applicant also failed to address the IDS statement in their reply, it is noted that the IDS filed 11/27/2024 fails to comply with 37 CFR 1.98(a)(2), no copies of the Non-Patent Literature documents or the Foreign references cited are present in the application, and therein have not been considered. Applicant’s amendments overcome claim objections, 112(b) rejections, and double patenting rejections, and 35 U.S.C. 103 rejections as set forth in the Non-Final Office Action dated 04/30/2026.
Response to Arguments
Applicant's arguments filed 08/31/2026 have been fully considered but they are not persuasive.
Applicant argues The combination of Clohset and ICS fails to disclose or suggest a respective programmable ray operation state indicator comprised in each of one or more nodes of the plurality of nodes as recited in Claim 1.
Examiner replies Applicant’s argument is fully considered but is not persuasive. Clohset describes a respective programmable ray operation state indicator, this thread, interpreted as an indicator, is not mapped to be a part of a node. Clohset teaches an indication of a ray operation state, whether to run or block an intersection test. ICS teaches nodes comprising operation state attribute (visited), based on this Boolean attribute, an operation (traversal) is performed. One of ordinary skill in the art would have been motivated to combine the teachings of the references to have nodes comprising state indicators for ray operations. Claims have been remapped for clarity and accordance to the amendments, and the rejection has been maintained.
Further, In response to applicant's argument that combining the references would not selectively enable or disable a ray operation corresponding to the ray indicator as claimed, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Specification
The disclosure is objected to because it contains an embedded hyperlink and/or other form of
browser-executable code in paragraphs [0019], [0091], and [0109]. Applicant is required to delete the
embedded hyperlink and/or other form of browser-executable code; references to websites should be
limited to the top-level domain name without any prefix such as http:// or other browser-executable
code. See MPEP § 608.01.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6, 11-12, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over rejected under 35 U.S.C. 103 as being unpatentable over Clohset et al. (US 20150089156 A1), hereinafter referenced as Clohset in view of ICS (“ICS 46 Spring 2016 Notes and Examples: Graph Traversals”, 2016), hereinafter referenced as ICS.
Regarding Claim 1, Clohset discloses a ray tracing hardware acceleration device (Clohset: [Fig. 2], illustrates a hardware acceleration device; [0056], discloses Fig. 2 may be implemented in a GPU for accelerating ray tracing; see below), comprising:
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memory configured to store an acceleration structure comprising a plurality of nodes (Clohset: [0096], discloses a memory storing values such as an acceleration structure element; [0043]; discloses acceleration structure elements such as a KD-tree which is an acceleration structure comprising nodes <a type of graph>),
(Clohset: [0070], discloses a first thread with a block state and a running state based on a the state of the first thread, an instruction <operation>, will be run or blocked <indication of a first/second state>; [0068], discloses the BoxTest instruction <ray operation> can be from a first thread, however this would not occur if the first thread is in a block state <since it indicates a ray operation state, the first thread is interpreted as a programmable ray operation state indicator>, see [Figs. 5A and B]);
ray storage configured to store a ray operation indicator received by a processor (Clohset: [0018-0019], discloses a memory storing an operation code <interpreted as the ray operation indicator, because an opcode tells a CPU, indicates, what operation to execute> from a ray received from a processor);
traversal circuitry configured to traverse the acceleration structure according to the ray (Clohset: [0042], discloses a programmable computation unit <interpreted as traversal circuitry> used to emit a ray to be traversed in a 3-D scene), the traversing including, (Clohset: [0070], discloses selectively, based on the thread, either running <performing the intersection test> corresponding to the state, or not blocking the test <not performing the ray operation>);
and intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor (Closet: [Fig. 2], illustrates a ray tester at reference character 120 <interpreted as intersection detection circuitry>; [0057], discloses the ray tester can perform intersection testing <detects an intersection> for a ray with both acceleration structure elements and scene primitives; [0076], discloses the ray tester operates serially on unqueued tests <reads on during traversing> and the ray tester produces results of its test operations and returns information to the update unit, shown in [Figs. 8A and B], as reference character 150; [0046], discloses the update unit performs processing <therefore interpreted as processor>; [0043], discloses acceleration structure elements such as a KD-tree which is an acceleration structure comprising nodes <a type of graph>).
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Clohset fails to disclose
wherein one or more nodes of the plurality of nodes each comprises a respective programmable ray operation state indicator, the respective programmable ray operation state indicator having a first state or a second state;
the traversing including, for each node of the one or more nodes comprising the respective programmable ray operation state indicator, selectively, based on the value of the respective programmable state indicator of the each node, either performing a ray operation corresponding to the ray operation indicator or not performing the ray operation;
However, ICS discloses
structure comprising a plurality of nodes, wherein one or more nodes of the plurality of nodes each comprises a respective programmable ( [Pg. 4], discloses a graph <structure> with one or more nodes, where each node of the plurality of nodes comprises a visited value associated with the node, it is programmable because it is a Boolean value <first and second state> and is an operation state indicator because it indicates the state of the visited operation);
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the traversing including, for each node of the one or more nodes comprising the respective programmable (ICS: [Pg. 4], discloses a depth first traversal including, for each node comprising the visited value <operation state indicator>, selectively based on the value of the node being visited or not of the each node, either performing an operation corresponding to the visited value or not performing the operation, if the node has been visited it goes to the next node, if it has it marks as visited <the operation> and moved on);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the ray tracing acceleration hardware device disclosed by Clohset by utilizing the node attribute operation state indicator as taught by ICS. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to conditionally perform operations for computational efficiency.
Regarding Claim 21, it discloses similar limitations to the method of Claim 1 but as a system. As shown in the rejection, the combination of Clohset and ICS disclose the hardware device of Claim 1. The combination of Clohset and ICS further disclose a system (Clohset: [0014], discloses a system) comprising:
a processor configured to generate a ray including a ray operation indicator (Clohset: [0066], discloses programmable computation unit 2 <interpreted as a processor> produces an operation code <interpreted as a ray operation indicator>);
and a coprocessor connected to the processor (Closet: [Fig. 1], illustrates a Limited function processing circuit at reference character 9 <interpreted as the coprocessor> connected to the programmable computational unit at reference character 2 <interpreted as the processor>) and comprising: …
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Regarding Claim 2, the combination of Clohset and ICS discloses the hardware device of Claim 1. The combination of Clohset and ICS further disclose wherein
each said respective programmable ray operation state indicator has a value of true or false (ICS: [Pg. 4], discloses the visited flag for a node <interpreted at the respective programmable ray operation state indicator> is a Boolean value of true or false, true if the node has been visited and false if it has not).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset and ICS by setting the flag to true or false as further disclosed by ICS. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to ensure that node representing complicated scenes are not visited multiple times.
Regarding Claim 6, the combination of Clohset and ICS discloses the limitations of Claim 1. The combination of Clohset and ICS further disclose(s) wherein
the not performing the ray operation comprises ignoring the ray operation with respect to said each node (ICS: [Pg. 4], discloses moving to the next node if the node is marked as visited, it does not perform the operation of marking the node as visited).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset and ICS by not performing an operation if a node is in a certain state as further disclosed by ICS . One of ordinary skill in the art before the effective filing date would have been motivated to make this modification to avoid repeated operations on the same node.
Regarding Claim 11, the combination of Clohset and ICS discloses the limitations of Claim 1. The combination of Clohset and ICS further disclose wherein the selectively not performing the ray operation comprises
traversing a child node of the each node without performing the ray operation on the child node (Clohset: [0064], discloses a thread <ray operation state indicator> can generate test operations represented by operation codes to be performed by a ray tester <ray operation>; [0070], discloses a status of a first thread being changed to a block state and a scheduler may swap in another thread, if the first thread is blocked, a different thread is scheduled to run instead <traversal does not perform the operation>).
Regarding Claim 12, the combination of Clohset and ICS discloses the limitations of Claim 1. The combination further discloses wherein the selectively performing the ray operation comprises
determining, based on the performed ray operation whether to traverse a child node of the each node, and responsive to a result of the determining either traversing the child node or not traversing the child node (Clohset: [0070], discloses a thread in a running state; [0064], discloses the performed operation may correspond to a type of ray testing performing during ray traversal <performed ray operation>; [0071], discloses the performed operation would be implemented to determine whether a box is a lead node that bounds primitives or not, if it does, it generates an operation to cause the ray to be tested against the set of primitives <ray operation>, if not, an operation code will be generated to test the ray against a set of child acceleration structure elements <interpreted as child nodes>).
Regarding Claim 14, the combination of Clohset and ICS discloses the limitations of Claim 1. The combination further discloses wherein
ray operation state indicator, wherein the respective programmable ray operation state indicator encodes a default action, wherein the respective programmable ray operation state indicator encodes a default action, and wherein the traversal circuitry is further configured to, when the respective programmable ray operation state indicator is in the second state, perform the default action, instead of performing the ray operation, at the each element (Clohset: [0078], discloses determining if a node is a leaf node by checking a flag; [0071], discloses an operation test <default action> to determine whether a box is a leaf node that bounds primitives or not, depending on this an operation code is generated to test a ray against a box. If not, an operation code will test the ray against a set of child acceleration structure elements).
a data structure of the each node includes the respective programmable (ICS: [Pg. 4], discloses where each node has a flag <data structure of the each node includes the respective programmable operation state indicator>).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device taught by the combination of Clohset and ICS by having the data structure include nodes, each with a flag, as further taught by ICS. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to identify nodes with distinct states to improve traversal efficiency.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Clohset and ICS in view of Xu (US 20200104635 A1), hereinafter referenced as Xu.
Regarding Claim 7, the combination of Clohset and ICS discloses the limitations of Claim 1. The combination of Clohset and ICS further disclose wherein the performing a ray operation corresponding to the ray operation indicator comprises
the ray operation specified by the ray operation indicator (Clohset: [0070] discloses performing a BoxTest <ray operation> specified by the opcode <ray operation indicator>)
The combination of Clohset and ICS do not disclose
performing the ray operation specified by the ray operation indicator on one or more child nodes of the each node
However, Xu discloses
performing the (Xu: [0054], discloses a preorder traversal where when a node that has not been visited <operation indicator> is visited <operation>, it’s child nodes have not been visited and therefore will be traversed; [Fig. 6] illustrates the preorder traversal, where [0054] discloses the order “F3NP20X!--F3NP--F3--F--3--NP--N--P--20X!--20--2--0--X!--X--!”, no child node was visited before the parent node).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset and ICS by performing an operation on the one or more child nodes of each node as taught by Xu. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to perform and operation on each node of the tree, ensuring all child nodes are acted on for completeness.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Clohset and ICS in view of Brown et al. (US 20080122845 A1), hereinafter referenced as Brown in further view of Aila et al. (US 8072454 B1), hereinafter referenced as Aila.
Regarding Claim 16, the combination of Clohset and ICS discloses the limitations of Claim 1. The combination of Clohset and ICS do not disclose the limitations of Claim 16, however, Brown discloses wherein
whereas the detecting of the one or more intersections is based on x, y and z coordinates associated with the each node of the acceleration structure and the ray, (Brown: [Fig. 4], illustrates calculating ray intersections using a 3D coordinate system with x, y, and z coordinates of acceleration structure elements and the ray; [0014], discloses ray tracing where nodes represent bounding volumes <nodes of the acceleration structure>).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset and ICS by using x, y, and z coordinates to detect ray intersections as taught by Brown. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to precisely calculate intersections.
The combination of Clohset, ICS, and Brown do not disclose
the ray operation is based on parameters other than the x, y and z coordinates associated with the each node
However, Aila discloses
the ray operation is based on parameters other than the x, y and z coordinates associated with the each node (Aila: [Col 8, ln 64], discloses a ray intersection with a primitive <ray operation> is based on parameters of ray length and distance to a node)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset, ICS, and Brown by supplementally basing a ray operation on ray length and distance to a node as taught by Aila. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to provide a mathematical operation to calculate ray intersections in 3D space with a node from the acceleration structure with precision.
Regarding Claim 17, the combination of Clohset, ICS, Brown, and Aila disclose the limitations of Claim 16. The combination of Clohset and ICS further disclose wherein
the parameters in the ray includes a length of the ray (Aila: [Col 8, ln 64], discloses the parameters in the ray includes a length of the ray).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset, ICS, Brown, and Aila by having the parameters of the ray include the length of the ray as further taught by Aila. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification for accurate intersection calculation and ray termination.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Clohset and ICS in view of Hagland (US 20210158597 A1), hereinafter referenced as Hagland.
Regarding Claim 19, the combination of Clohset and ICS discloses the hardware device of Claim 1. The combination of Clohset and ICS further disclose(s)
wherein the traversal circuitry and the intersection detection circuitry are used for ray tracing (Clohset: [0042], [0046], [0057], [0070], [0076], [Fig. 2], and [Figs. 8A and B], disclose traversal circuitry and intersection circuitry for ray tracing)
The combination of Clohset and ICS do not disclose
Ray tracing implementations are parts of a server or a data center employed in generating an image, and the image is streamed to a user device (Hagland: [0036], discloses ray tracing used to render at least a portion of a frame for a scene of a game which is executed by the game engine; [0096], discloses a server or a data center executing a game engine which is rendered on a client device, see [Fig. 7]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset and ICS by implementing the ray tracing on a server or data center then streaming the generated image to a user device as taught by Hagland. One of ordinary skill in the art would have been motivated to make this modification to allow a user device of lesser power to display the rendered ray traced images while using a more powerful external system, such as a server or a data center, to perform the actual computationally expensive ray tracing.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Clohset and ICS in view of Gurvich et al. (US 20190303725 A1), hereinafter referenced as Gurvich.
Regarding Claim 20, the combination of Clohset and ICS discloses the hardware device of Claim 1. The combination of Clohset and ICS further disclose
the traversal circuitry and the intersection detection circuitry are employed in ray tracing (Clohset: [0042], [0046], [0057], [0070], [0076], [Fig. 2], and [Figs. 8A and B], disclose traversal circuitry and intersection circuitry employed in ray tracing)
The combination of Clohset and ICS do not disclose
Ray tracing employed in generating an image, and the image is used for training, testing, or certifying a neural network employed in a machine, robot, or autonomous vehicle
However, Gurvich disclose(s) wherein
Ray tracing employed in generating an image, and the image is used for training(Gurvich: [0080], discloses ray tracing used to generate a modified image and the image is used for training a neural network).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the hardware device disclosed by the combination of Clohset and ICS by using ray tracing for generating an image to be used for training a neural network employed in a machine as taught by Gurvich. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification because more training data enhances the robustness of the model, and improves the ability of the neural network to analyze features from the detected images.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Clohset in view of ICS, in further view of Woop et al. (US 20210287428 A1), hereinafter referenced as Woop, and in further view of Williams et al. (US 20200134200 A1), hereinafter referenced as Williams.
Regarding Claim 22, Clohset discloses a method (Clohset: [0006], discloses a memory), comprising:
storing in a memory (Clohset: [0096], discloses a memory storing values such as an acceleration structure element; [0043]; discloses acceleration structure elements such as a KD-tree which is an acceleration structure comprising nodes <a type of graph>; [0071], discloses child elements of an acceleration structure);
receiving, (Clohset: [0018-0019], discloses a memory storing an operation code <interpreted as the ray operation indicator, because an opcode tells a CPU, indicates, what operation to execute> from a ray received from a processor);
storing the ray operation indicator in a ray storage in the hardware coprocessor (Clohset: [0018-0019], discloses a memory <ray storage> storing an operation code <interpreted as the ray operation indicator>);
traversing, by traversal circuitry in the hardware coprocessor, the acceleration structure according to the ray, (Clohset: [0042], discloses a programmable computation unit <interpreted as traversal circuitry in a hardware coprocessor, Fig. 2 illustrates multiple programmable computation units> used to emit a ray to be traversed in a 3-D scene);
and detecting, by intersection detection circuitry in the hardware coprocessor, one or more intersections of the ray with one or more acceleration structure elements of the acceleration structure during the traversing and return information of the detected intersection to the processor (Closet: [Fig. 2], illustrates a ray tester at reference character 120 <interpreted as intersection detection circuitry>; [0057], discloses the ray tester can perform intersection testing <detects an intersection> for a ray with both acceleration structure elements and scene primitives; [0076], discloses the ray tester operates serially on unqueued tests <reads on during traversing> and the ray tester produces results of its test operations and returns information to the update unit, shown in [Figs. 8A and B], as reference character 150; [0046], discloses the update unit performs processing <therefore interpreted as processor>; [0064], discloses the processing circuits may be subdivided among two or more circuits <reads as hardware coprocessor>).
Clohset does not disclose
a memory in a hardware coprocessor
one or more nodes
structure comprising a plurality of nodes, each node of the plurality of nodes comprises a respective programmable ray operation state indicator
the traversing including, for each element comprising the respective programmable ray operation state indicator, selectively, based on a value of the respective programmable ray operation state indicator of the each node, either performing a ray operation corresponding to the ray operation indicator or not performing the ray operation
an acceleration structure comprising a compressed treelet including a node
However, ICS discloses
structure comprising a plurality of nodes, each node of the plurality of nodes comprises a respective programmable (ICS: [Pg. 4], discloses a graph <structure> with one of more nodes, where each node of the plurality of nodes comprises a visited value associated with the node, it is programmable because it isa Boolean value and is an operation state indicator because it indicates the state of the visited operation)
the traversing including, for each node comprising the respective programmable node, either performing a (ICS: [Pg. 4], discloses a depth first traversal including, for each node comprising the visited value <operation state indicator>, selectively based on the value of the node being visited or not of the each node, either performing an operation corresponding to the visited value or not performing the operation, if the node has been visited it goes to the next node, if it has it marks as visited <the operation> and moved on)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the method disclosed by Clohset by using a state indicator to decide whether or not an operation is performed as taught by ICS. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to mark the state of a node in efforts to avoid redundant calculations.
The combination of Clohset and ICS do not disclose
an acceleration structure comprising a compressed treelet including a node
a memory in a hardware coprocessor
However, Woop discloses
acceleration structure comprising a compressed treelet including a node (Woop: [0257], discloses a compressed-leaf bounding volume hierarchy (CLBVH) which is an acceleration structure that compresses leaf nodes <treelet including a node, a leaf constitutes as a single node treelet>)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the method disclosed by the combination of Clohset and ICS by storing a CLBVH as taught by Woop. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to significantly reduce memory.
The combination of Clohset, ICS, and Woop do not disclose
a memory in a hardware coprocessor
However, Williams discloses
a memory in a hardware coprocessor (Williams: [0033], discloses a memory inside a security processor in hardware included in a secure environment; [0034], discloses tis security processor is separate from the main processor <reads on hardware coprocessor>)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply and/or modify the method disclosed by combination of Clohset, ICS, and Woop by having a memory inside a hardware coprocessor as disclosed by Williams. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make this modification to boost system performance, enabling high-bandwidth, low-latency access to data.
Allowable Subject Matter
Claims 3-5, 8-10, 13, 15, and 18 are objected to as being dependent upon a rejected base claim,
but would be allowable if rewritten in independent form including all of the limitations of the base claim
and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior references on the record, alone or in combination fail to explicitly disclose wherein the acceleration structure comprises a first bottom level acceleration structure (BLAS) and second BLAS, wherein one of the first BLAS and the second BLAS has at least one level of detail (LOD) of geometry that is not in the other of the first BLAS and the second BLAS, and the respective programmable ray operation state indicator of the first BLAS has a value different from that of the respective programmable ray operation state indicator of the second BLAS.
Regarding Claim 4, the prior references on the record, alone or in combination fail to explicitly disclose wherein said each of the one or more node nodes of the plurality of nodes comprising a respective programmable ray operation state indicator is in a respectively different compressed treelet comprising said each node and one or more child nodes of said each node.
Claim 5 is objected to based on dependency to Claim 4.
Regarding Claim 8, the prior references on the record, alone or in combination fail to explicitly disclose wherein the performing a ray operation corresponding to the ray operation indicator comprises performing, using the ray operation indicator, at least one parameter specified in the ray other than the ray operation indicator, and at least one parameter specified in a child node of the each node, the ray operation specified by the ray operation indicator.
Regarding Claim 9, the prior references on the record, alone or in combination fail to explicitly disclose wherein the respective programmable ray operation state indicator is stored in a complet including the each node and one or more child nodes of the each node, and wherein the each node includes a node parameter that is used in the ray operation with one or more other parameters from the ray.
Regarding Claim 10, the prior references on the record, alone or in combination fail to explicitly disclose wherein the respective programmable ray operation state indicator is set in the each node, and wherein the traversal circuitry is further configured to, if the respective programmable ray operation state indicator is in the second state, determining, based on an invert bit in a child node of the each node, whether or not to traverse the child node without performing the ray operation on the child node.
Regarding Claim 13, the prior references on the record, alone or in combination fail to explicitly disclose wherein a data structure of the each node includes the respective programmable ray operation state indicator, and wherein the traversal circuitry is further configured to perform the ray operation using the ray operation indicator, and at least one parameter specified in the ray other than the ray operation indicator and/or at least one parameter specified in a child node of the each node.
Regarding Claim 15, the prior references on the record, alone or in combination fail to explicitly disclose wherein the each node is a root node in a compressed treelet and the each node includes a node parameter that is used in the ray operation with one or more parameters from the ray.
Regarding Claim 18, the prior references on the record, alone or in combination fail to explicitly disclose wherein the respective programmable ray operation state indicator is set in the each node, and wherein the traversal circuitry is further configured to, if the respective programmable ray operation state indicator is in the second state has a second value, determining, based on an invert bit in a child node of the each node, whether or not to traverse the child node of the each node without performing the ray operation on the child node.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISABELLA OCHSNER whose telephone number is (571)272-9322. The examiner can normally be reached 9:30 - 6:00 PM.
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/I.O./Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618
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