CTNF 18/962,783 CTNF 74833 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending and examined. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 Claim s 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-24 of copending Application No. 17/648,403 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they both recite limitations of reading data from non-sequential column addresses concurrently . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 112 07-34-01 Claims 3-5, 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 recites limitation “wherein the at least one activation command is received consecutively ” on lines 1-2. It is not clear to Examiner how to interpret this limitation. For purpose of examination, Examiner temporary does not consider the recited limitation. Claim 11 recite limitation “wherein the at least one activation command is received consecutively ” on line 1-2. Same rejection above applies. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by PGPub. 2022/0399060 to Lu et al. (hereafter Lu) . Regarding independent claim 1 , Lu teaches a memory device, comprising: a memory array ( FIG. 1: memory array 102 ) comprising a row of memory cells coupled with a set of multiplexers ( FIG. 2: first MUX associated with BLEN1<i>, see paragraph [0033] ); and one or more controllers ( FIG. 8: e.g. first controller 806 ) coupled with the memory array and the set of multiplexers, the one or more controllers operable to cause the memory device to: activate a word line for the row of memory cells based on receiving at least one activation command ( e.g. selecting a word line in response to an inherent active command which latches and decodes row address, see paragraphs [0034] ); transfer respective voltages stored at the memory cells of the row to digit lines for the memory cells based on activating the word line, the respective voltages indicative of logic values stored at the memory cells ( e.g. retrieving data from bit cells, see paragraphs [0036] and [0043] ); communicate a respective control signal to each multiplexer of a set of multiplexers coupled with the digit lines ( signals BLEN1<i> associated with first MUX, see paragraph [0033] ), wherein each multiplexer is coupled with a subset of noncontiguous digit lines ( because all bit lines of a column slice may not be adjacent to each other, see paragraph [0032] ); and sense a plurality of logic values from memory cells coupled with a respective plurality of noncontiguous digit lines based on communicating the respective control signals ( FIG. 2: via sense amplifiers SA 108, see paragraph [0033] ). Regarding dependent claim 2 , Lu teaches wherein, to sense the plurality of logic values, the one or more controllers are further configured to cause the memory device to: couple a first digit line from each subset of noncontiguous digit lines with a respective sense component of a set of sense components based on a respective control signal ( FIG. 2: e.g. when BLEN<1> is enable, first MUX coupled first bit line of the column slice to SA ); sense a voltage from each first digit line based on coupling the first digit line with the respective sense component, the voltage indicative of a logic value stored at a memory cell associated with the first digit line; and latch the voltage from each first digit line ( latch the voltage from first line using sample and hold circuit, see paragraphs [0050]-[0051] ). Regarding dependent claim 3 , Lu teaches wherein the one or more controllers are further configured to cause the memory device to: receiving, after receiving the at least one activation command, at least one read command indicating address information ( read command, see paragraph [0036] ), wherein transferring the respective voltages is based on the address information ( because each bit line is in response to a column address, see paragraph [0034] ). Regarding dependent claim 4 , Lu teaches wherein the one or more controllers are further configured to cause the memory device to: communicate, over a data bus, the plurality of logic values based on receiving the at least one read command, wherein each logic value of the plurality of logic values is associated with a respective digit line of the plurality of noncontiguous digit lines ( FIG. 3: output Dout ). Regarding dependent claim 5 , Lu teaches wherein the address information comprises a plurality of non-sequential column addresses associated with memory cells of the plurality of noncontiguous digit lines ( because all bit lines of a column slice may not be adjacent to each other, see paragraph [0032] ). Regarding dependent claim 6 , Lu implicitly teaches wherein, to communicate the respective control signals, the one or more controllers are further configured to cause the memory device to: communicate a first control signal to a first multiplexer of the set of multiplexers, the first control signal having a first value; and communicate a second control signal to a second multiplexer of the set of multiplexers, the second control signal having a second value different than the first value ( when the column slices of a computing array come in different size, the corresponding first MUX of unequal column slices should require different numbers of BLEN<i> signals, see paragraph [0032] ). Regarding dependent claim 7 , Lu implicitly teaches wherein, to communicate the respective control signals, the one or more controllers are further configured to cause the memory device to: communicate a third control signal to a third multiplexer of the set of multiplexers, the third control signal having a third value different than at least one of the first value or the second value ( e.g. in case a third column slice comes in different size from first and second column slices ). Regarding dependent claim 8 , Lu teaches wherein the at least one activation command indicates address information for the memory cells, and wherein values for each control signal are based on the address information ( FIG. 2: BLEN<i> is generated in response to column address, see paragraph [0034] ). Regarding independent claim 9 , Lu teaches a method by a memory device, comprising: activating a word line for a row of memory cells of a memory array based on receiving at least one activation command( e.g. selecting a word line in response to an inherent active command which latches and decodes row address, see paragraphs [0034] ); transferring respective voltages stored at the memory cells of the row to digit lines for the memory cells based on activating the word line, the respective voltages indicative of logic values stored at the memory cells ( e.g. retrieving data from bit cells, see paragraphs [0036] and [0043] ); communicating a respective control signal to each multiplexer of a set of multiplexers coupled with the digit lines ( signals BLEN1<i> associated with first MUX, see paragraph [0033] ), wherein each multiplexer is coupled with a subset of noncontiguous digit lines ( because all bit lines of a column slice may not be adjacent to each other, see paragraph [0032] ); and sense a plurality of logic values from memory cells coupled with a respective plurality of noncontiguous digit lines based on communicating the respective control signals ( FIG. 2: via sense amplifiers SA 108, see paragraph [0033] ). Regarding dependent claims 10-16 , see rejection applied to claims 2-8 above. Regarding independent claim 17 , Lu teaches a non-transitory computer-readable medium storing processor-executable code ( FIG. 16: software 1612 ), the code comprising instructions executable by one or more processors ( FIG. 16: processor 1602 ) to: activate a word line for a row of memory cells of a memory array based on receiving at least one activation command ( e.g. selecting a word line in response to an inherent active command which latches and decodes row address, see paragraphs [0034] ); transfer respective voltages stored at the memory cells of the row to digit lines for the memory cells based on activating the word line, the respective voltages indicative of logic values stored at the memory cells ( e.g. retrieving data from bit cells, see paragraphs [0036] and [0043] ); communicate a respective control signal to each multiplexer of a set of multiplexers coupled with the digit lines ( signals BLEN1<i> associated with first MUX, see paragraph [0033] ), wherein each multiplexer is coupled with a subset of noncontiguous digit lines ( because all bit lines of a column slice may not be adjacent to each other, see paragraph [0032] ); and sense a plurality of logic values from memory cells coupled with a respective plurality of noncontiguous digit lines based on communicating the respective control signals ( FIG. 2: via sense amplifiers SA 108, see paragraph [0033] ). Regarding dependent claims 18-20 , see rejection applied to claims 2-4 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. 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June 15, 2026 /VANTHU T NGUYEN/Primary Examiner, Art Unit 2824 Application/Control Number: 18/962,783 Page 2 Art Unit: 2824 Application/Control Number: 18/962,783 Page 3 Art Unit: 2824 Application/Control Number: 18/962,783 Page 4 Art Unit: 2824 Application/Control Number: 18/962,783 Page 5 Art Unit: 2824 Application/Control Number: 18/962,783 Page 6 Art Unit: 2824 Application/Control Number: 18/962,783 Page 7 Art Unit: 2824 Application/Control Number: 18/962,783 Page 8 Art Unit: 2824 Application/Control Number: 18/962,783 Page 9 Art Unit: 2824
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