Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 27 November 2024 for application number 18/962,815. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 30 November 2023 (Provisional 63/604,756).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 27 November 2024 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 9 – 11, 12, 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsern [hereafter as Tsern], US Pub. No. 2007/0033338 A1 in view of Hwang et al. [hereafter as Hwang], US Pub. No. 2016/0133314 A1.
As per claim 1, Tsern discloses a method of operation in a dynamic random access memory (DRAM) device [“A method of operation within a dynamic random access memory (DRAM) device”] [claim 1], the method comprising:
receiving, by the DRAM device from a controller, a refresh type indicating a refresh procedure for refreshing one or more rows of a memory cell array of the DRAM device [“the storage arrays within the memory devices 125.sub.0-125.sub.n or any one of them may be organized in separately addressable storage banks, with each of B banks containing a respective set of X rows.”] [para. 0044] [“The method of clause 11 wherein generating refresh commands directed to the first row of storage cells comprises generating a first number of first-type refresh commands during a refresh interval and wherein generating refresh commands directed to the second row of storage cells comprises generating a second, different number of second-type refresh commands during the refresh interval.”] [para. 0135];
storing the refresh type in refresh control circuity of the DRAM device [“storing the information within a memory controller to enable the memory controller to provide the address of the second row in association with the refresh commands issued to the memory device to effect the second refresh rate.”] [para. 0160]; and
performing the row refresh of the DRAM device according to the refresh type stored in the refresh control circuity [“The method of clause 11 wherein generating refresh commands directed to the first row of storage cells comprises generating a first number of first-type refresh commands during a refresh interval and wherein generating refresh commands directed to the second row of storage cells comprises generating a second, different number of second-type refresh commands during the refresh interval.”] [para. 0135].
However, Tsern does not explicitly disclose refresh type flag.
Hwang teaches a refresh type flag [“The refresh control circuit 300 may transmit a short-pulsed type refresh flag signal RFG to the memory controller through the refresh pins 204 and 104.”] [para. 0143].
Tsern and Hwang are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Tsern with Hwang in order to modify Tsern for “a refresh type flag” as taught by Hwang. One of ordinary skill in the art would be motivated to combine Tsern with Hwang before the effective filing date of the claimed invention to improve a system by providing for the ability where an “input/output controller hub … may perform data buffering and interface arbitration in order to efficiently operate various system interfaces.” [Hwang, para. 0178].
Claim 11 is rejected with like reasoning.
As per claim 2, Tsern in view of Hwang discloses the method of claim 1, Tsern discloses wherein receiving the refresh type comprises:
receiving a data access command to access a row of the memory cell array of the DRAM device, wherein the data access command includes the refresh type [“The method of clause 11 wherein generating refresh commands directed to the first row of storage cells comprises generating a first number of first-type refresh commands during a refresh interval and wherein generating refresh commands directed to the second row of storage cells comprises generating a second, different number of second-type refresh commands during the refresh interval.”] [para. 0135].
Hwang teaches refresh type flag [“The refresh control circuit 300 may transmit a short-pulsed type refresh flag signal RFG to the memory controller through the refresh pins 204 and 104.”] [para. 0143].
Claim 12 is rejected with like reasoning.
As per claim 6, Tsern in view of Hwang discloses the method of claim 1, Hwang teaches wherein the refresh procedure corresponds to a refresh normal procedure [normal refresh operation], a relaxed refresh procedure, or a no refresh procedure [“FIG. 14 illustrates that the normal refresh operation”] [para. 0132].
Claim 15 is rejected with like reasoning.
As per claim 9, Tsern in view of Hwang discloses the method of claim 1, Hwang teaches wherein performing the row refresh of the DRAM device according to the refresh type flag stored in the refresh control circuity is further based on at least one of a refresh counter, a row hammer control, or Partial Array Self Refresh (PASR) bits [“In example embodiments, the refresh control circuit may include a refresh clock generator, a refresh counter, a weak page address generator, an address comparing circuit, a control signal generator, an address converter and a refresh address output circuit. The refresh clock generator may generate a refresh clock signal in response to a first refresh control signal, a second refresh control signal and a mode signal. The refresh counter may generate counting address for sequentially refreshing the memory cell rows in response to the refresh clock signal, the refresh counter outputting a done signal upon generating a maximum counting address.”] [para. 0015].
Claim 18 is rejected with like reasoning.
As per claim 10, Tsern in view of Hwang discloses the method of claim 1, Tsern discloses further comprising:
receiving a refresh command to execute a second row refresh of the DRAM device [“The method of clause 11 wherein generating refresh commands directed to the first row of storage cells comprises generating a first number of first-type refresh commands during a refresh interval and wherein generating refresh commands directed to the second row of storage cells comprises generating a second, different number of second-type refresh commands during the refresh interval.”] [para. 0135]; and
gating, using the refresh control circuitry, the refresh command to prevent the second row refresh of the memory cell array [“prevent refresh operations from being performed in response to secondary refresh commands that result in selection of an unused register 191”] [para. 0063].
Claim 19 is rejected with like reasoning.
Claims 3, 8, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsern [hereafter as Tsern], US Pub. No. 2007/0033338 A1 in view of Hwang et al. [hereafter as Hwang], US Pub. No. 2016/0133314 A1 as applied to claims 1, 2, and 11 above, and further in view of Riho et al. [hereafter as Riho], US Pub. No. 2005/0169083 A1.
As per claim 3, Tsern in view of Hwang discloses the method of claim 2, Hwang teaches refresh type flag [“The refresh control circuit 300 may transmit a short-pulsed type refresh flag signal RFG to the memory controller through the refresh pins 204 and 104.”] [para. 0143].
However, Tsern and Hwang do not explicitly disclose wherein the refresh type is at least 2 bits of the data access command.
Riho teaches wherein the refresh type is at least 2 bits of the data access command [“In the present embodiment, one of four types of the refresh periods, specified by two bits, is set per sub-word line (8K) of 16 memory arrays. That is, the refresh period type information is set in terms of a sub-word line of each memory cell array of the bank 100.”] [para. 0092].
Tsern, Hwang, and Riho are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Tsern and Hwang with Riho in order to modify Tsern and Hwang “wherein the refresh type is at least 2 bits of the data access command” as taught by Riho. One of ordinary skill in the art would be motivated to combine Tsern and Hwang with Riho before the effective filing date of the claimed invention to improve a system by providing for the ability where “it is desired that the self-refresh period be extended within such a range that data in the memory cells can be maintained and that self-refreshing be performed for all the memory cells by a specific optimal period.” [Riho, para. 0007].
As per claim 8, Tsern in view of Hwang discloses the method of claim 1, Hwang teaches refresh type flag [“The refresh control circuit 300 may transmit a short-pulsed type refresh flag signal RFG to the memory controller through the refresh pins 204 and 104.”] [para. 0143].
However, Tsern and Hwang do not explicitly disclose wherein the refresh control circuity comprises a refresh type per Word Line (WL) configuration, a refresh type per main WL configuration, or a refresh type per matrix row configuration.
Riho teaches wherein the refresh control circuity comprises a refresh flag per Word Line (WL) configuration, a refresh type per main WL configuration, or a refresh type per matrix row configuration [“If there are 16 memory arrays, each comprising 512 bit line pairs, 16.times.2=32 bit cells are arranged per each word line WLR in the RAM 101 for 16 sub-word lines connected to a sole main word line. In the present embodiment, one of four types of the refresh periods, specified by two bits, is set per sub-word line (8K) of 16 memory arrays. That is, the refresh period type information is set in terms of a sub-word line of each memory cell array of the bank 100.”] [para. 0092].
Tsern, Hwang, and Riho are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Tsern and Hwang with Riho in order to modify Tsern and Hwang “wherein the refresh type is at least 2 bits of the data access command” as taught by Riho. One of ordinary skill in the art would be motivated to combine Tsern and Hwang with Riho before the effective filing date of the claimed invention to improve a system by providing for the ability where “it is desired that the self-refresh period be extended within such a range that data in the memory cells can be maintained and that self-refreshing be performed for all the memory cells by a specific optimal period.” [Riho, para. 0007].
Claim 17 is rejected with like reasoning.
Claims 4, 5, 13, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsern [hereafter as Tsern], US Pub. No. 2007/0033338 A1 in view of Hwang et al. [hereafter as Hwang], US Pub. No. 2016/0133314 A1 as applied to claims 1 and 11 above, and further in view of Mobley [hereafter as Mobley], US Pub. No. 2002/0147885 A1.
As per claim 4, Tsern in view of Hwang discloses the method of claim 1, Tsern discloses wherein receiving the refresh type comprises:
receiving, via a command interface of the DRAM device, a data access command to access a row of the memory cell array of the DRAM device [“The method of clause 11 wherein generating refresh commands directed to the first row of storage cells comprises generating a first number of first-type refresh commands during a refresh interval and wherein generating refresh commands directed to the second row of storage cells comprises generating a second, different number of second-type refresh commands during the refresh interval.”] [para. 0135] [para. 0050]; and
receiving, during a burst time associated with the data access command, the refresh type via one or more inputs of the DRAM device, wherein the one or more inputs are separate from the command interface [“the increment logic 185a includes a comparator 197 having inputs to receive a bank address (BA) from the command interface 173 and an increment address 192 ("incr addr"), and an output coupled to a first input of an AND gate 191. The second input of the AND gate 191 is coupled to receive the primary refresh signal, Ref1.”] [para. 0055].
Hwang teaches refresh type flag [“The refresh control circuit 300 may transmit a short-pulsed type refresh flag signal RFG to the memory controller through the refresh pins 204 and 104.”] [para. 0143].
However, Tsern and Hwang do not explicitly disclose receiving, during a burst time associated with the data access command, the refresh type.
Mobley teaches receiving, during a burst time associated with the data access command, the refresh type [“…refresh is performed serially as compared to the row filling operation. (This type of refresh operation is referred to hereinafter as a "serial refresh operation.") By extending the number of words (or bits) output in any burst, the number of rows that can be serially refreshed per burst increases.”] [para. 0028].
Tsern, Hwang, and Mobley are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Tsern and Hwang with Mobley in order to modify Tsern and Hwang “wherein the refresh type is at least 2 bits of the data access command” as taught by Mobley. One of ordinary skill in the art would be motivated to combine Tsern and Hwang with Mobley before the effective filing date of the claimed invention to improve a system by providing for the ability where “refresh operations can be performed without risking that a read request will interrupt the refresh operation.” [Mobley, Abstract].
Claim 13 is rejected with like reasoning.
Claim 20 is rejected with like reasoning as claims 1, 11, 4, and 13 above, except for the following remaining claim limitations:
A controller integrated circuit (IC) device.
Tsern discloses a controller integrated circuit (IC) device [“Also, the expression "memory device" is generally used herein to refer to an integrated circuit die (or package containing same) having predominantly a data storage function, though a memory device may include additional circuitry on the same die or within the same package, for example, to perform a memory controller function or other control function. The term "memory" alone refers broadly to a memory system or memory device.”] [para. 0028].
As per claim 5, Tsern in view of Hwang and further in view of Mobley discloses the method of claim 4, Hwang teaches wherein the one or more inputs of the DRAM device correspond to at least one of a data mask input (DMI) or a read data strobe signal (RDQS) [“The input/output gating circuit 290 may further include an input data mask logic”] [para. 0084].
Claim 14 is rejected with like reasoning.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tsern [hereafter as Tsern], US Pub. No. 2007/0033338 A1 in view of Hwang et al. [hereafter as Hwang], US Pub. No. 2016/0133314 A1 as applied to claims 1 and 11 above, and further in view of Jung [hereafter as Jung], US Pub. No. 2024/0202328 A1.
As per claim 7, Tsern in view of Hwang discloses the method of claim 1, however Tsern and Hwang do not explicitly disclose wherein the refresh control circuity comprises one or more latches, and further comprising:
receiving, from the controller, a command to initialize the one or more latches to a default value; and
initializing the one or more latches to the default value responsive to receiving the command.
Jung teaches wherein the refresh control circuity comprises one or more latches [“More specifically, the refresh control circuit 540 may include a refresh latch 542,”] [para. 0096], and further comprising:
receiving, from the controller, a command to initialize the one or more latches to a default value [“wherein the address latch circuits are configured to be initialized whenever the refresh management command is input k times, where k is a natural number.”] [claim 4]; and
initializing the one or more latches to the default value responsive to receiving the command [“wherein the address latch circuits are configured to be initialized whenever the refresh management command is input k times, where k is a natural number.”] [claim 4].
Tsern, Hwang, and Jung are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Tsern and Hwang with Jung in order to modify Tsern and Hwang “wherein the refresh control circuity comprises one or more latches, and further comprising:
receiving, from the controller, a command to initialize the one or more latches to a default value; and
initializing the one or more latches to the default value responsive to receiving the command” as taught by Jung. One of ordinary skill in the art would be motivated to combine Tsern and Hwang with Jung before the effective filing date of the claimed invention to improve a system by providing for the ability where “The processor … may change the order in which the request REQ is received from the host and the order of the operation to be instructed to the memory device 100 to improve the performance of the memory device ...” [Jung, para. 0036].
Claim 16 is rejected with like reasoning.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135