DETAILED ACTION
This non-final action is responsive to communications: application filed on 11/27/2024. Applicant’s preliminary amendment filed on 02/10/2025 is being acknowledged and entered.
Claims 2-21 are pending. Claim 2, and 12 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic DIV priority details.
Information Disclosure Statement
5. IDS filed on 02/10/2025 has been considered.
Drawings
6. Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Official Notice is taken regarding the fact that Figure 1 was previously used by the applicant in other applications/ patents which are prior arts and Figure 1 is conventional.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
7. The disclosure is objected to because of the following informalities:
Applicant’s specification paragraphs 0011-0025 associated sections describe details of “typical” memory device. As described above, Figure 1 should be designated as --Prior Art--. Therefore, paragraphs 0011-0025 and associated sections, and the other descriptions of prior art and problems, should be under the Background of the Invention section of Applicant’s Specification because the description of the related art or other information disclosed known to the applicant belongs in the Background of the Invention section, see MPEP 608.01(c) (the Specification’s Background is for description of the state of the prior art or other information known to applicant and problems involved in the prior art or other information which are solved by applicant’s invention.”).
Applicant is reminded of helpful scenario 7 explained in MPEP 2004 and encouraged to take care to see that prior art or other information cited in a specification or in an information disclosure statements is properly described and that the information is not incorrectly or incompletely characterized.
Appropriate correction is required.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Interpretation
Although claims 2-11 are recited as a method of “forming” and manufacturing, claims do not recite substantive fabrication steps, details and are indistinct from apparatus structure other than the mere presentation of language of method of forming instead of a device. Similarly, claims 12-21 are directed towards device structures since they are written in product by process format. For claims 2-21 method/ steps of forming a device is not germane to the issue of patentability of the device itself. Thus, claims 2-21 are interpreted without giving patentable weight for forming limitation; and claims 2-21 are interpreted as directed to structures of the claimed device.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 2, 5, 8-9, 12, 15, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OH (US 2022/0108999 A1).
Regarding independent claim 2, OH teaches a method (fabricating Fig. 2 structure. See attached Examiner’s Markup version of OH Figure 2) comprising:
forming a stack of material layers (Fig. 2: US) over a substrate of a memory die (Fig. 2: 10 “substrate”),
the stack of material layers (Fig. 2: US) comprising alternating layers (para [0042]: “…WL2 that are stacked alternately with a plurality of interlayer dielectric layers…”), along a first direction away from the substrate (Fig. 2: Z-direction), of a first material (para [0042]: “dielectric layer”; Fig. 2: 22B) and a second material (Fig. 2: WL2, see para [0042]-para [0043]: WL conductor),
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the second material comprising a semiconductor material (para [0042]-para [0043]: WL conductor with “doped semiconductor”);
forming a plurality of word line conductors (Fig. 2: A-D) arranged in a stack (para [0045], para [0049]; Fig. 2: LS) along the first direction (Fig. 2: Z-direction),
each word line conductor of the plurality of word line conductors (para [0049]: WL1/ SP1, Fig. 2: A-D) operable to access (operably connected to cells in string) a respective set of one or more memory cells (Fig. 2 in context of para [0044]-para [0046]);
forming a plurality of first portions of the second material (Fig. 2: P1-2nd with contacts) based at least in part (partly based on) on removing the second material through a layer of the second material from around each first portion (Fig. 2: formation of contact conductors require removal of WL conductor material in circular fashion around inner diameter of the columns),
each first portion of the second material (Fig. 2: P1-2nd) electrically coupled with a respective word line conductor of the plurality of word line conductors (Fig. 2: each P1-2nd is coupled to A, B, C, D of the “staircase” word lines);
forming a plurality of second portions of the second material (Fig. 2: Fig. 2: P2-2nd with contacts) based at least in part on (partly based on) removing the second material through the layer of the second material from around each second portion (Fig. 2: formation of contact conductors require removal of WL conductor material in circular fashion around inner diameter of the columns); and
forming a gate material portion (Fig. 2: DSL gates) operable to modulate (modulate taken as a change) a conductivity (bias applied on DSL gates impacts conductivity of P1-2nd region, P2-2nd region, combined region since they are conductively connected) between each first portion of the plurality of first portions of the second material (Fig. 2: P1-2nd regions) and a respective second portion of the plurality of second portions of the second material (Fig. 2: P2-2nd regions) based at least in part on a voltage of the gate material portion (Fig. 2: based on applied bias conductivity in CP2 would be changed due to voltage difference).
Regarding claim 5, OH teaches the method of claim 2, further comprising: forming a respective electrical coupling between each first portion of the second material and the respective word line conductor based at least in part on forming a respective cavity coincident with the respective word line conductor (See Fig. 2: contact regions connecting A, B, C, D to P1-2nd regions)
and depositing a conductive material in the respective cavity (See Fig. 2: conductive pillars connecting A, B, C, D to P1-2nd regions)
Regarding claim 8, OH teaches the method of claim 2, wherein each word line conductor is operable to access a respective plurality of memory cells that are associated with (coupled with) a respective layer of the second material (Fig. 2: word lines coupled to memory cells in different Z-direction levels of the string which are again coupled to different layers in US).
Regarding claim 9, OH teaches the method of claim 2, further comprising: forming an electrical coupling between each second portion of the plurality of second portions of the second material (Fig. 2: P2-2nd) and a word line driver circuit (Fig. 1: 121 is operably connected to word lines and its different components).
Regarding independent claim 12, OH teaches an apparatus formed by a process comprising: forming a stack of material layers over a substrate of a memory die, the stack of material layers comprising alternating layers, along a first direction away from the substrate, of a first material and a second material, the second material comprising a semiconductor material; forming a plurality of word line conductors arranged in a stack along the first direction, each word line conductor of the plurality of word line conductors operable to access a respective set of one or more memory cells; forming a plurality of first portions of the second material based at least in part on removing the second material through a layer of the second material from around each first portion, each first portion of the second material electrically coupled with a respective word line conductor of the plurality of word line conductors; forming a plurality of second portions of the second material based at least in part on removing the second material through the layer of the second material from around each second portion; and forming a gate material portion operable to modulate a conductivity between each first portion of the plurality of first portions of the second material and a respective second portion of the plurality of second portions of the second material based at least in part on a voltage of the gate material portion.
(Claimed limitations are substantially identical to claim 2 and claim is rejected for the same reason as claim 2. Prior art device teaches all the structures claimed in claim #12. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966).
Regarding claim 15, OH teaches the apparatus of claim 12, the process further comprising: forming a respective electrical coupling between each first portion of the second material and the respective word line conductor based at least in part on forming a respective cavity coincident with the respective word line conductor and depositing a conductive material in the respective cavity. (See claim 5 rejection analysis)
Regarding claim 18, OH teaches the apparatus of claim 12, wherein each word line conductor is operable to access a respective plurality of memory cells that are associated with a respective layer of the second material. (See claim 8 rejection analysis)
Regarding claim 19, OH teaches the apparatus of claim 12, the process further comprising: forming an electrical coupling between each second portion of the plurality of second portions of the second material and a word line driver circuit. (See claim 9 rejection analysis)
Allowable Subject Matter
Claims 3-4, 6-7, 10-11, 13-14, 16-17, and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Further, any associated double patenting rejection must be over-come.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
US 12,131,794 B2 claims 15-25 are applicable for nonstatutory double patenting rejections against claims 1-11 of instant application. Applicant is encouraged to file a Terminal Disclaimer to expedite prosecution.
Park (US 2024/0065004 A1): Fig. 1-Fig. 15 applicable for all claims.
Xue (US 2022/0068797 A1): Fig. 1-Fig. 7 applicable for all claims.
Young et al. (US 2022/0278128 A1): Young teaches an apparatus (“…three-dimensional memory device…”, see Fig. 3A-Fig. 3D), comprising: a plurality of word line conductors (Fig. 3C: 104-1…104-4) arranged in a stack along a first direction (Fig. 3C: z-direction) away from a substrate of a memory die (Fig. 3C: 300), each word line conductor of the plurality of word line conductors (Fig. 3C: 104-1…104-4) extending along a second direction over the substrate (Fig. 3C: y-direction) and operable to access a respective set of one or more memory cells over the substrate (para [0032]: MC); a plurality of first portions of a semiconductor material (Fig. 3C: SD coupled to WR1-3 in T. See four of these arranged) arranged along the second direction (Fig. 3C: y-direction), each first portion of the semiconductor material electrically coupled with a respective word line conductor of the plurality of word line conductors (See WR1-3 coupled to SD in T. Similarly, see WR1-1, WR2-4, WR2-2 coupled to SD’s); and a gate material portion (Fig. 3C: GE in T “gate electrode”) operable to modulate a respective conductivity between each first portion of the semiconductor material (Fig. 3C: SD coupled to WR1-3 in T) and a respective second portion of a plurality of second portions of the semiconductor material (Fig. 3C: uncoupled SD in T) over the substrate based at least in part on a voltage of the gate material portion (para [0044]: gate electrode of FET and function).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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