DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1 – 15 in the reply filed on 07/07/2026 is acknowledged.
Claims 16 and 17 are considered withdrawn without traverse.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 3 and 7 – 15 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Philpott et al. (US Pat 9,939,827).
Regarding claim 1, Philpott et al. disclose an apparatus (figs. 1 – 11 and all related texts), comprising:
a configuration memory cell (20, fig. 3), the configuration memory cell including:
a first connection point (for example node 28-1 via BL, fig. 3) to control access of one or more storage nodes of the configuration memory cell (access transistors 58 controlling storage node X, fig. 3. See also col. 6, lines 8 – 21);
a second connection point (for example node 28-2 via nBL, fig. 3) to manage stability of one or more of the storage nodes of the configuration memory cell during access of the configuration memory cell (the complimentary bitline nBL to help manage stability of the storage node nX during access/read/write operations of the memory cell. See col. 6, lines 22 – 46); and
a third connection point to control voltage transitions at one or more storage nodes of the configuration memory cell during access of the configuration memory cell (referred to as node 50 to receive power supply voltage Vcch, which varies in time depending on current operating temperature. See col. 5, lines 52 – 65).
Claims 11 and 12 are also considered a parallel method claim to that of the apparatus claim 1. Therefore, claim 11 is also rejected based on functionality prior arts by Philpott et al. as shown above.
Regarding claim 2, Philpott et al. also disclose the apparatus of claim 1, wherein the configuration memory cell (20 of fig. 3) includes a transistor (58) to selectively couple a bit line (BL) to one or more of the storage nodes (X) of the configuration memory cell responsive to the first connection point (gate of transistor 58, fig. 3).
Regarding claims 3 and 15, Philpott et al. also disclose he apparatus of claim 1, wherein the configuration memory cell includes a transistor to control how strongly a bit line influences one or more storage nodes of the configuration memory cell responsive to the third connection point (see col. 5, line 52 – col. 6, line 7; and col. 6, line 64 – col. 8, line 4. Temperature dependent power supply voltage varies the power supply voltage Vcch effecting the configuration cell drive strength).
Regarding claims 7 and 14, Philpott et al. also disclose the apparatus of claim 1 (further shown in fig. 5), wherein the configuration memory cell includes a transistor to provide stability to one or more storage nodes of the configuration memory cell by selectively modulating current flow to or from the one or more storage nodes (referred to as current drawing circuit coupled between node 140 and ground line, fig. 5), the modulation of current flow at least partially based on a signal received via the second connection point (col. 10, lines 3 – 18, “help maintain stability of regulator 134”).
Regarding claims 8 and 13, Philpott et al. also disclose the apparatus of claim 1, comprising: a high-resistance element (for example transistor 36, fig.3) coupled between a storage node of the one or more storage nodes (node nX, fig. 3) and an output of the configuration memory cell to enhance single-event upset (SEU) resistance (effectively inherent for enhancing the claimed SEU).
Regarding claim 9, Philpott et al. also disclose the apparatus of claim 1, wherein the configuration memory cell includes a first inverter and a second inverter cross-coupled between a first node and a second node to store state information represented by complementary voltages at the first node and the second node (referred to as the cross-coupled latch 54 and 56, fig. 3, wherein X and nX are complementary node voltages of the storage cell 20).
Regarding claim 10, Philpott et al. also disclose the apparatus of claim 9, wherein transistors of one or more of the first inverter or second inverter exhibit nonuniform voltage tolerance (fig. 7 shows Vcch variation due to temperature, for which, when view in fig. 3, the Vcch applied to the cross-coupled latches will inherently mean the transistors of the inverters in the cross-coupled latches must exhibit nonuniform voltage tolerance).
Allowable Subject Matter
Claims 4 – 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the apparatus as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 July 30, 2026
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