Prosecution Insights
Last updated: April 19, 2026
Application No. 18/963,185

CHIP, DYNAMIC VISION SENSOR, AND METHOD FOR OUTPUTTING PIXEL INFORMATION

Non-Final OA §103
Filed
Nov 27, 2024
Examiner
DAGNEW, MEKONNEN D
Art Unit
2638
Tech Center
2600 — Communications
Assignee
Institute Of Semiconductors Chinese Academy Of Sciences
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
604 granted / 728 resolved
+21.0% vs TC avg
Strong +16% interview lift
Without
With
+15.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
29 currently pending
Career history
757
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
63.7%
+23.7% vs TC avg
§102
21.5%
-18.5% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 728 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 3-10, 13-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Niwa (US 20210385404 A1) in view of Berner (US 20190052820 A1). As of Claim 1: Niwa teaches a chip, comprising a pixel array (¶0053 exhibit a pixel array unit 300) and a processing circuit, wherein each pixel row in the pixel array comprises at least two pixel groups, and each pixel group of the at least two pixel groups comprises a plurality of pixels (¶0054 exhibit the pixel array unit 300, a plurality of pixels 310 is arrayed in a two-dimensional lattice manner. Hereinafter, a set of the pixels arrayed in a horizontal direction is referred to as a “row”, and a set of the pixels arrayed in a direction perpendicular to the row is referred to as a “column”); the processing circuit is configured to: based on detecting that a light value of at least one pixel in a first pixel group changes (¶¶0049,0055 and note that the pixel detects the presence or absence of an address event according to whether or not a change amount of an incident light amount has exceeded a predetermined threshold. Then, when an address event has occurred, the pixel outputs a request to the arbiter 213. Then, when receiving a response to the request, the pixel transmits a detection signal indicating a detection result of the address event to the drive circuit 211 and the signal processing unit 212.), generate a first signal, wherein the first signal comprises row location information of the first pixel group in the pixel array, and the first pixel group is any pixel group in the pixel array; generate a second signal, wherein the second signal comprises column location information of a pixel row in which the first pixel group is located; and send the first signal and the second signal to a pixel output circuit, wherein the first signal and the second signal are used to enable the pixel output circuit to output location information of the first pixel group whose light intensity value changes in the pixel array (¶¶0073 and note that the light-receiving unit 330 includes two connection nodes, one of which is connected to the address event detection unit 400 and the other of which is connected to the pixel signal generation unit 320. Furthermore, the light-receiving units 330 in four rows×two columns are commonly connected to one pixel signal generation unit 320, and the light-receiving units 330 in two rows×four columns are commonly connected to one address event detection unit 400. The light-receiving units 330 in four rows×two columns and the pixel signal generation unit 320 connected thereto form the FD shared block 301. Meanwhile, the light-receiving units 330 in two rows×four columns and the address event detection unit 400 connected thereto form the detection block 302.). Berner is a similar or analogous system to the claimed invention as evidenced Berner teaches vision sensor comprising, an array of pixels (101) comprising rows and columns of pixels, wherein each pixel has an address assigned thereto which represents the position of the pixel in the array, wherein each pixel in the array of pixels comprises a photodiode (103) which can receive light, and which can output current having an amplitude proportional to the intensity of the received light that would have prompted a predictable variation of Niwa by applying Berner’s known principal of based on detecting that a light intensity value of at least one pixel in a first pixel group changes (¶¶0001,0164,0192 and note that the pixel value (meaning a value representing the light intensity of this pixel) may optionally be output to the processor; instead the addresses of those pixels where a change is detected are transmitted. To detect changes between now and a previous moment in time, each pixel stores a representation of the light intensity at this previous moment in time (called illum_last)). In view of the motivations such as accurate reading of pixel locations with the change detected thereby efficiently encoding visual input; allowing to externally control pixel and thus sensor timing; and controlling the sensor time resolution and thus the rate at which a pixel can output information and reducing jitter in the readout path as disclosed in ¶0063 of Berner and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Niwa. Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention. As of Claim 3: Niwa in view of Berner further teaches the pixel array comprises M*N pixels, M is a quantity of rows of the pixel array, N is a quantity of columns of the pixel array, and both M and N are positive integers (¶0109 of Berner and note that the vision sensor of FIG. 3a further comprises a circuit 202 for selecting one or multiple rows (called row selection circuit), where selection means selectively connect the pixels in this row to the corresponding column circuit; and a circuit 203 for transmitting the addresses of those pixels where the difference between Vpr and Vpr_last exceeds a predefined threshold). As of Claim 4: Niwa in view of Berner further teaches the processing circuit is configured to: based on a changed light intensity value of a pixel in the first pixel group being greater than a preset threshold (¶¶0164, 0192 of Niwa and note that the pixel array unit 21 includes a plurality of pixels 30. The plurality of pixels 30 outputs output signals in response to a selection signal from the readout area selection unit 27. The configuration of each of the plurality of pixels 30 is similar to that of the pixel 310 illustrated in FIG. 4. The plurality of pixels 30 outputs output signals corresponding to the change amount of light intensity. The plurality of pixels 30 may be two-dimensionally arranged in a matrix as illustrated in FIG. 25), determine that the light intensity value of the pixel changes, wherein the preset threshold is any value from 5% of the pixel light intensity value to 30% of the pixel light intensity value (¶¶0164, 0192 of Berner). As of Claim 5: Niwa in view of Berner further teaches the first signal of the processing circuit indicates that the light intensity value of the first pixel group changes (¶¶0164, 0192 of Niwa). As of Claim 6: Niwa in view of Berner further teaches the processing circuit is configured to: send a light intensity value of each pixel in the first pixel group to the pixel output circuit using the first signal or the second signal, to enable the pixel output circuit to output the light intensity value of each pixel in the first pixel group (¶¶0121,0139,0164 of Berner and note that signals (EventOn) indicates increasing light intensity, the other one (EventOff) indicates decreasing light intensity. There is an OR-gate 1803 with its inputs connected to the outputs of the Flip-Flop and its output connected to an AND-gate 1804.). As of Claim 7: Niwa in view of Berner further teaches the processing circuit is configured to: determine a pixel signal of each pixel in the first pixel group, wherein a pixel signal of a first pixel in the first pixel group indicates whether a light intensity value of the first pixel changes (¶¶0121,0139,0164 of Berner and note that signals (EventOn) indicates increasing light intensity, the other one (EventOff) indicates decreasing light intensity. There is an OR-gate 1803 with its inputs connected to the outputs of the Flip-Flop and its output connected to an AND-gate 1804.) , and the first pixel is any pixel in the first pixel group; and perform logical computation on the pixel signal of each pixel in the first pixel group to obtain the first signal (¶0109 of Berner and note that the vision sensor of FIG. 3a further comprises a circuit 202 for selecting one or multiple rows (called row selection circuit), where selection means selectively connect the pixels in this row to the corresponding column circuit; and a circuit 203 for transmitting the addresses of those pixels where the difference between Vpr and Vpr_last exceeds a predefined threshold). As of Claim 8: Niwa in view of Berner further teaches the processing circuit is configured to: after sending the first signal to the pixel output circuit, receive a response signal sent by the pixel output circuit that is of the first signal; and send the second signal to the pixel output circuit based on the response signal of the first signal (¶¶0121,0139,0164 of Berner and note that signals (EventOn) indicates increasing light intensity, the other one (EventOff) indicates decreasing light intensity. There is an OR-gate 1803 with its inputs connected to the outputs of the Flip-Flop and its output connected to an AND-gate 1804.) As of Claim 9: Niwa in view of Berner further teaches the chip further comprises a row arbitration circuit (¶0057 of Niwa and note that the arbiter 213 arbitrates requests from the pixels and returns a response on the basis of an arbitration result.), wherein the row arbitration circuit is configured to: determine, based on the row location information comprised in the first signal that is of the first pixel group in the pixel array and row location information comprised in a third signal that is of a second pixel group in the pixel array, a sequence of processing the first signal and the third signal; and process the first signal and the third signal based on the sequence, wherein the third signal indicates that a light intensity value of the second pixel group changes, and the second pixel group and the first pixel group belong to different pixel rows (¶¶0121,0139,0164 of Berner and note that signals (EventOn) indicates increasing light intensity, the other one (EventOff) indicates decreasing light intensity. There is an OR-gate 1803 with its inputs connected to the outputs of the Flip-Flop and its output connected to an AND-gate 1804.). As of Claim 10: Niwa in view of Berner further teaches the row arbitration circuit comprises a subarbiter and a processor, wherein the subarbiter is configured to determine, based on the row location information comprised in the first signal that is of the first pixel group in the pixel array and the row location information comprised in the third signal that is of the second pixel group in the pixel array (¶¶0055-0057 of Niwa and note thatThe pixel in the pixel array unit generates an analog signal as a pixel signal by photoelectric conversion. Furthermore, the pixel detects the presence or absence of an address event according to whether or not a change amount of an incident light amount has exceeded a predetermined threshold. Then, when an address event has occurred, the pixel outputs a request to the arbiter 213. Then, when receiving a response to the request, the pixel transmits a detection signal indicating a detection result of the address event to the drive circuit 211 and the signal processing unit 212.), the sequence of processing the first signal and the third signal; and the processor is configured to process the first signal and the third signal based on the sequence (¶¶0121,0139,0164 of Berner). As of Claim 13: Niwa in view of Berner further teaches the row arbitration circuit is configured to: determine, based on the row location information 00064-0067 of Niwa and note thatThe number of rows is 4N (N is an integer) and the number of columns is 4M (M is an integer). Furthermore, n is an integer of 1 to N and m is an integer of 1 to M, and attention is given to sixteen pixels in four rows×four columns. These sixteen pixels are divided by two FD shared blocks 301 and two detection blocks 302. One of the two FD shared blocks 301 is a left-side block, the other is a right-side block, one of the two detection blocks 302 is an upper-side block, and the other is a lower-side ). As of Claim 14: Niwa teaches a dynamic vision sensor (¶0002), comprising the chip and the pixel output circuit, wherein the chip comprises a pixel array and a processing circuit, each pixel row in the pixel array comprises at least two pixel groups (¶0053 exhibit a pixel array unit 300), and each pixel group of the at least two pixel groups comprises a plurality of pixels; the processing circuit is configured to: based on detecting that a light intensity value of at least one pixel in a first pixel group changes, generate a first signal, wherein the first signal comprises row location information of the first pixel group in the pixel array, and the first pixel group is any pixel group in the pixel array (¶0054 exhibit the pixel array unit 300, a plurality of pixels 310 is arrayed in a two-dimensional lattice manner. Hereinafter, a set of the pixels arrayed in a horizontal direction is referred to as a “row”, and a set of the pixels arrayed in a direction perpendicular to the row is referred to as a “column”); generate a second signal, wherein the second signal comprises column location information of a pixel row in which the first pixel group is located; and send the first signal and the second signal to a pixel output circuit, wherein the first signal and the second signal are used to enable the pixel output circuit to output location information of the first pixel group whose light intensity value changes in the pixel array (¶¶0049,0055 and note that the pixel detects the presence or absence of an address event according to whether or not a change amount of an incident light amount has exceeded a predetermined threshold. Then, when an address event has occurred, the pixel outputs a request to the arbiter 213. Then, when receiving a response to the request, the pixel transmits a detection signal indicating a detection result of the address event to the drive circuit 211 and the signal processing unit 212.)wherein the pixel output circuit comprises a row arbitration circuit and a column selection circuit, and a clock signal of the row arbitration circuit is synchronized with a clock signal of the column selection circuit; the row arbitration circuit (¶0057 and the arbiter 213 arbitrates requests from the pixels and returns a response on the basis of an arbitration result) is configured to: receive a first signal sent by a processing circuit in the chip, determine row location information of a first pixel group in a pixel array based on the first signal, and send the row location information of the first pixel group in the pixel array to the column selection circuit; and the column selection circuit is configured to: receive a second signal sent by the processing circuit, receive the row location information sent by the row arbitration circuit that is of the first pixel group in the pixel array, determine, based on the second signal, column location information of a pixel row in which the first pixel group is located, and output location information of the first pixel group in the pixel array (¶¶0073 and note that the light-receiving unit 330 includes two connection nodes, one of which is connected to the address event detection unit 400 and the other of which is connected to the pixel signal generation unit 320. Furthermore, the light-receiving units 330 in four rows×two columns are commonly connected to one pixel signal generation unit 320, and the light-receiving units 330 in two rows×four columns are commonly connected to one address event detection unit 400. The light-receiving units 330 in four rows×two columns and the pixel signal generation unit 320 connected thereto form the FD shared block 301. Meanwhile, the light-receiving units 330 in two rows×four columns and the address event detection unit 400 connected thereto form the detection block 302.). Berner is a similar or analogous system to the claimed invention as evidenced IKI teaches would have prompted a predictable variation of Niwa by applying Berner’s known principal of based on detecting that a light intensity value of at least one pixel in a first pixel group changes (¶¶0001,0164,0192 and note that the pixel value (meaning a value representing the light intensity of this pixel) may optionally be output to the processor; instead the addresses of those pixels where a change is detected are transmitted. To detect changes between now and a previous moment in time, each pixel stores a representation of the light intensity at this previous moment in time (called illum_last)). In view of the motivations such as accurate reading of pixel locations with the change detected thereby efficiently encoding visual input; allowing to externally control pixel and thus sensor timing; and controlling the sensor time resolution and thus the rate at which a pixel can output information and reducing jitter in the readout path as disclosed in ¶0063 of Berner and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Niwa. Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention. As of Claim 16: Niwa teaches FIG. 13 a method for outputting pixel information by a dynamic vision sensor (¶¶0127), wherein the method comprises: based on detecting that value of at least one pixel in a first pixel group changes, generating a first signal and a second signal, wherein the first pixel group is any pixel group in a pixel array; determining row location information of the first pixel group in the pixel array based on the first signal (¶¶028-0129,0168), and determining, based on the second signal, column location information of a pixel row in which the first pixel group is located; and outputting location information of the first pixel group in the pixel array based on the row location information of the first pixel group in the pixel array and the column location information of the pixel row in which the first pixel group is located (¶¶0065-0066). Berner is a similar or analogous system to the claimed invention as evidenced Berner teaches vision sensor comprising, an array of pixels (101) comprising rows and columns of pixels, wherein each pixel has an address assigned thereto which represents the position of the pixel in the array, wherein each pixel in the array of pixels comprises a photodiode (103) which can receive light, and which can output current having an amplitude proportional to the intensity of the received light that would have prompted a predictable variation of Niwa by applying Berner’s known principal of based on detecting that a light intensity value of at least one pixel in a first pixel group changes (¶¶0001,0164,0192 and note that the pixel value (meaning a value representing the light intensity of this pixel) may optionally be output to the processor; instead the addresses of those pixels where a change is detected are transmitted. To detect changes between now and a previous moment in time, each pixel stores a representation of the light intensity at this previous moment in time (called illum_last)). In view of the motivations such as accurate reading of pixel locations with the change detected thereby efficiently encoding visual input; allowing to externally control pixel and thus sensor timing; and controlling the sensor time resolution and thus the rate at which a pixel can output information and reducing jitter in the readout path as disclosed in ¶0063 of Berner and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Niwa. As of Claim 17: Niwa in view of Berner further teaches after the generating a first signal and a second signal, the method further comprises: determining a light intensity value of each pixel in the first pixel group based on the first signal or the second signal, and outputting the light intensity value of each pixel in the first pixel group (¶¶0164, 0192 of Berner). As of Claim 18: Niwa in view of Berner further teaches the method further comprises: based on detecting that a light intensity value of at least one pixel in a second pixel group changes, generating a third signal, wherein the second pixel group and the first pixel group belong to different pixel rows (¶¶0121,0139,0164 of Berner and note that signals (EventOn) indicates increasing light intensity, the other one (EventOff) indicates decreasing light intensity. There is an OR-gate 1803 with its inputs connected to the outputs of the Flip-Flop and its output connected to an AND-gate 1804.) ; determining row location information of the second pixel group in the pixel array based on the third signal; and determining, based on the row location information of the first pixel group and the row location information of the second pixel group in the pixel array, a sequence of outputting the first pixel group and the second pixel group (¶¶0164, 0192 of Berner) As of Claim 19: Niwa in view of Berner further teaches the first signal is generated using the following manner: determining a pixel signal of each pixel in the first pixel group, wherein a pixel signal of a first pixel in the first pixel group indicates whether a light intensity value of the first pixel changes, and the first pixel is any pixel in the first pixel group; and performing logical computation on the pixel signal of each pixel in the first pixel group to obtain the first signal (¶¶0121,0139,0164 of Berner and note that signals (EventOn) indicates increasing light intensity, the other one (EventOff) indicates decreasing light intensity. There is an OR-gate 1803 with its inputs connected to the outputs of the Flip-Flop and its output connected to an AND-gate 1804.) As of Claim 20: Niwa in view of Berner further teaches the method further comprises: when outputting the location information of the first pixel group whose light intensity value changes in the pixel array, outputting a timestamp corresponding to the first pixel group (¶¶0173 of Niwa and note that the signal generation unit 28 outputs address information and time stamp information (for example, (X, Y, T)) of the active pixel in which the event is detected through an output line 15. Note that data output from the signal generation unit 28 may be not only the address information and the time stamp information but also frame format information (for example, (0, 0, 1, 0, . . . ))). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Niwa (US 20210385404 A1) in view of Berner (US 20190052820 A1), and further in view of Brändli et al. (US 20220239851 A1; hereafter Brändli). As of Claim 2: Brändli is a similar or analogous system to the claimed invention as evidenced Brändli teaches dynamic vision sensor such as an event based vision sensor employs analog to digital converters (ADC), such as ramp ADCs, that analog to digital converts the signals from photoreceptors that would have prompted a predictable variation of Niwa by applying Brändli’s known principal of a quantity of pixel groups comprised in each pixel row in the pixel array is determined in the following manner: for each preset initial quantity of groups, determining (¶0047), based on a column quantity of the pixel array, a bit width of pixel data, and a quantity of first pixel groups in the pixel array, an amount of pixel data corresponding to the initial quantity of groups; and determining that an initial quantity of groups corresponding to a minimum amount of pixel data in each amount of pixel data is the quantity of pixel groups comprised in each pixel row (¶¶0096). In view of the motivations such as accurate reading of pixel locations with the change detected thereby efficiently encoding visual input; allowing to externally control pixel and thus sensor timing; and controlling the sensor time resolution and thus the rate at which a pixel can output information and reducing jitter in the readout path as disclosed in ¶0063 of Berner and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Niwa. Allowable Subject Matter Claims 11, 12, 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As of Claim 11 : the prior art of record fails to teach or fairly suggest the limitations of claim 11, combination with claims 1, that includes, “wherein the chip further comprises a row arbitration circuit, wherein the row arbitration circuit is configured to: receive the first signal and at least one third signal sent by the processing circuit, wherein the third signal indicates that a light intensity value of a second pixel group changes, and the second pixel group and the first pixel group belong to different pixel rows; separately generate the response signal of the first signal and a response signal of the third signal; determine a first sequence of sending the response signal of the first signal and the response signal of the third signal to the processing circuit; and send the response signal of the first signal and the response signal of the third signal to the processing circuit based on the first sequence, to enable the processing circuit to send the second signal to the pixel output circuit; and send a fourth signal to the pixel output circuit, wherein the fourth signal comprises column location information of the pixel row in which the second pixel group is located.” As of Claim 12: Claim 12 depends on Claim 11 and objected as Allowable subject matter as well. As of Claim 15 : the prior art of record fails to teach or fairly suggest the limitations of claim 15, combination with claims 14, that includes, “wherein the row arbitration circuit is further configured to: receive at least one third signal sent by the processing circuit, wherein the third signal indicates that a light intensity value of a second pixel group changes, and the second pixel group and the first pixel group belong to different pixel rows, separately generate a response signal of the first signal and a response signal of the third signal, determine a first sequence of sending the response signal of the first signal and the response signal of the third signal to the processing circuit, and send the response signal of the first signal and the response signal of the third signal to the processing circuit based on the first sequence; and the processing circuit is further configured to: after receiving the response signal sent by the row arbitration circuit that is of the first signal, send the second signal to the column selection circuit, and after receiving the response signal sent by the row arbitration circuit that is of the third signal, send a fourth signal to the column selection circuit, wherein the fourth signal comprises column location information of the pixel row in which the second pixel group is located.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEKONNEN D DAGNEW whose telephone number is (571)270-5092. The examiner can normally be reached on 8:00AM-5:00PM M-Th. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEKONNEN D DAGNEW/Primary Examiner, Art Unit 2638
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Prosecution Timeline

Nov 27, 2024
Application Filed
Apr 08, 2025
Response after Non-Final Action
Mar 21, 2026
Non-Final Rejection — §103 (current)

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