DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over America et al (US 2006/0040501) in view of Hsieh et al (US 7,585,778) and further in view of Han et al (US 2022/0392765).
Regarding claim 1, America et al disclose a process of making an integrated structure (a damascene conductor structure) (see the abstract) that corresponds to the claimed” packaging substrate”, wherein the process comprises preparing the structure 10 having a base substrate 11, and an insulating layer (low K ILD;14) and an organic layer (Ol,16) is disposed on the insulating layer (see Figure 1A); [0022]).
America et al disclose a patterning step of selectively plasma etching the insulating (low-K ILD; interlayer dielectric) (see Figure 1H; wherein the Organic Layer (OL) is formed as an intermediate sacrificial masking layer above locations where a future trench area is to be formed during formation of vias the ILD layer [0008].
America et al also disclose etching of the siloxane dielectrics (used as low k ILD layer[0006]) is most commonly carried out with an RF plasma using gases having a fluorocarbon, e.g. C.sub.4F.sub.8, C.sub.5F.sub.6, C.sub.5F.sub.8, CF.sub.4, CHF.sub.3, CH.sub.2F.sub.2, CF.sub.3F, with argon, nitrogen, carbon dioxide and oxygen [0035].
America et al also disclose that the device 10 of FIG. 1M after completion of the process of this invention and continuing to form a dielectric liner layer 49L and filling with deposition of conductor metal 49M ([0047], Figure 1N).
America et al fail to disclose the etching or patterning is performed at a temperature of 120 degree C or less.
However, in the same field of endeavor, Hsieh et al disclose a plasma etching process for etching low-K dielectric (abstract); and the temperature and pressure of the etch reactor 102 are regulated during processing to maintain an environment suitable for etching the organic layer 204. The temperature may be controlled in a range of between about 0-60 degrees Celsius (col.5, lines 16-20); and aforesaid temperature range overlaps the claimed range of 120 degree C or less; and overlapping ranges are prima facie obvious, See MPEP 2144.05.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ Hsieh et al's teaching of introducing the controlled temperature into the teaching of America et al to maintain an environment suitable for etching the organic low-k dielectric material as taught by Hsieh et al.
Additionally, the selection of reaction parameters such as temperature and concentration would have been obvious: "Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art. such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”. In re Aller 105 USPQ 233, 255 (CCPA 1955).See also In re Waite 77 USPQ 586 (CCPA 1948).
Unlike the instant invention, modified America et al fail to disclose a stabilization process of reducing the atmosphere temperature of the patterning step as required in the claim 1.
However, Han et al disclose a plasma etching process of interlevel dielectric (ILD) [0078]; and also disclose that process parameters such as temperature may be controlled independently at each step of the cyclic plasma process in accordance with the respective process recipe [0083]; and the substrate is kept at a temperature between 5° C. and 120° C. In some embodiments, temperature may be changed at each step of the cyclic plasma process, and purge steps are used to stabilize the system prior to generating a plasma. In alternate embodiments, temperature may be programmed to be ramped or cooled during the plasma steps, that is, the time intervals, T2 and T4 [0084].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ Han et al's teaching of changing or reducing the substrate etching temperature to stabilizing the system into the teaching of modified America et al for stabilizing the processing/etching temperature as well as stabilizing the processing system as taught by Han et al.
Regarding claim 2, America et al disclose that the etching mask (organic layer 16) is disposed in contact with an upper surface of the low K ILD, 14 (corresponding the claimed insulating layer) (see Figure 1E).
Regarding claim 3, Han et al disclose that the etching and the purging steps used to stabilizing the system [0084] ; and next cycle of four time intervals may be performed. The cycle may be repeated any number of times to achieve a desired process performance [0089].
Regarding claim 4, without showing any criticality of such duration, one of ordinary skill in the art would easily optimize the claimed duration of the etching for achieving a desired process performance as taught by Han et al [0089].
Regarding claim 5, America et al disclose etching of the siloxane dielectrics (used as low k ILD layer[0006]) is most commonly carried out with an RF plasma using gases having a fluorocarbon, e.g. C.sub.4F.sub.8, C.sub.5F.sub.6, C.sub.5F.sub.8, CF.sub.4, CHF.sub.3, CH.sub.2F.sub.2, CF.sub.3F, with argon, nitrogen, carbon dioxide and oxygen [0035].
Regarding claim 6, America et al disclose that a plasma is generated during etching and the amount of power which is applied to the electrodes is of the level of 500 watts and 100 watts for the 27 MHz and for the 2 MHz frequencies, respectively [0029]; However, without showing any criticality of such power level, one of ordinary skill in the art would easily optimize the claimed power level of the etching for desired etching rate by routine experimentation.
Regarding claim 7, the thickness of the mask can be optimized for predictable result.
Regarding claim 9, America et al disclose that a through hole (47) being formed in the insulating layer ( low K ILD) (see figure 1L) and the claimed diameter would have been optimized as the diameter of the through hole be determined by the type of semiconductor device to be formed .
Regarding claim 10, America et al disclose that the device 10 of FIG. 1M after completion of the process of this invention and continuing to form a dielectric liner layer 49L and filling with deposition of conductor metal 49M ([0047], Figure 1N); and the peel strength of the upper conductive layer would have been encompassing as the conductor metal being formed in the through hole.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over America et al (US 2006/0040501) in view of Hsieh et al (US 7,585,778) and in view of Han et al (US 2022/0392765) as applied to claim 1 above, and further in view of Yamazaki et al (US 2021/0242345).
Modified America et al disclose above for the claim 1 but fail to disclose a cleaning step after the patterning or etching step before the manufacturing step using ultrasonic cleaning.
However, Yamazaki et al disclose a semiconductor device manufacturing process [0183], [0269]; and it is preferable to remove impurities that are attached onto the surfaces of the oxides 230a and 230b or diffused into the oxide 230a and the oxide 230b, for example. The impurities result from components contained in the insulator 280, the insulating film 254A, and the conductive layer 242B; components contained in a member of an apparatus used to form the opening; and components contained in a gas or a liquid used for etching, for instance [0278].
Yamazaki et al also disclose that it is known that when the frequency more than or equal to 10 kHz and 200 kHz is applied to a liquid in the ultrasonic cleaning, vibration acceleration of the molecule in a liquid is small but cavitation is generated a lot; the higher the frequency becomes, the larger the vibration acceleration of the molecule in a liquid becomes and cavitation generation decreases. Therefore, the frequency for the ultrasonic cleaning can be determined in consideration of the cleaning effect and the damage to a semiconductor device to be cleaned [0103].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ Yamazaki et al's teaching of cleaning impurities after the etching/patterning step into the teaching of modified America et al for achieving a cleaner substrate’s surface for subsequent process that is advantageous as suggest by Yamazaki et al.
Conclusion
The prior art made of record, listed in the PTO-892 and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAMIM AHMED whose telephone number is (571)272-1457. The examiner can normally be reached M-TH (8-5:30pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
SHAMIM AHMED
Primary Examiner
Art Unit 1713
/SHAMIM AHMED/ Primary Examiner, Art Unit 1713
Prosecution Insights