DETAILED ACTION
Response to Amendment
This action is responsive the amendment filed on 3/5/2026. Claims 1-15 are pending and have been examined. Claims 1, 8-9 and 15 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretations
Claim 9 recites the following contingent limitations: “…wherein the operating system write the current task identification of the current task into a current ID buffer in response to a key owned by the current task being correct; comparing the current task identification with a previous branch task identification to generate a comparison result by a secure branch prediction circuit in response to the current task performing branch prediction of a branch instruction; and outputting a jump prediction message or a non-jump prediction message by the secure branch prediction circuit based on the comparison result”.
The contingent limitations use the language “in response to” which are contingent because they are only required to be performed “in response to” (e.g. if) a condition is being met (e.g. writing a current ID buffer only occurs if a key owned by the task is correct, comparing and outputting based on the comparing only occur if a current task performs branch prediction of a branch instruction). However, if a key owned is incorrect no write would occur and if a current task of a processor does not perform branch prediction because a branch instruction is not being performed the following steps are not required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)). Therefore, the broadest reasonable interpretation of claim 9 is “A secure branch prediction method, comprising: executing an operating system by a user core circuit to request the operating system to assign a current task identification to a current task while the current task is created”. For purposes of examination the examiner will provide a prior art rejection with the above broadest reasonable interpretation.
The examiner suggests amending the claim to remove the contingent limitations stating “in response to” to positively recite each step of the method claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 8 and 15 contain the trademark/trade name “FreeRTOS™”. Where a trademark or trade name is used in a claim as a limitation to identify or describe a particular material or product, the claim does not comply with the requirements of 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. See Ex parte Simpson, 218 USPQ 1020 (Bd. App. 1982). The claim scope is uncertain since the trademark or trade name cannot be used properly to identify any particular material or product. A trademark or trade name is used to identify a source of goods, and not the goods themselves. Thus, a trademark or trade name does not identify or describe the goods associated with the trademark or trade name. In the present case, the trademark/trade name is used to identify/describe an embedded system operating system and, accordingly, the identification/description is indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Evers, USPAT No. 11,734,011, Luo, PGPUB No. 2024/0134683, Solomatnikov, PGPUB No. 2022/0292183, and further in view of Wang, PGPUB No. 2014/0068232.
In regards to claim 1, Evers discloses A processor with secure branch prediction function (See Fig. 1: wherein a processor system (element 100) is disclosed (see Column 2, lines 34-61 and details of Fig. 3 which disclose details of secure branch prediction structure included in processor system which prevents inadvertent or intentional aliasing between different processes accessing the branch prediction structure)) comprising: generate a plurality of task identifications (TIDs) (Column 6, lines 12-16: wherein each time a process is executed or scheduled a context tag (e.g. a task identifier) is generated. Wherein a plurality of context tags would be generated, one for each of the different processes (See Fig. 2, element 215 which illustrates a plurality of context tags including a plurality of thread identifiers (element 230)) (see Colum 2, lines 58-67 to Column 3, lines 1-14 for further details on context identifier information)) wherein the task identifications comprise a current task identification and a previous branch task identification (Column 6, lines 13-16 and 60-64 and Column 8, lines 37-61: wherein context tags include a current process context tag and a previous context tag stored in the branch prediction structure) a user core circuit configured to execute an operating system (Column 4, lines 16-22 and Column 6, lines 12-16: wherein processor core of processing system executes operating system (element 110) (See Fig. 1)) and request the operating system to assign the current task identification to a current task while the current task is created (Column 6, lines 12-16 and Column 8, lines 9-37: wherein processor core, executing a current process, requests operating system assign context tag to a current process while the current process is created. Wherein operating system assigns context information from which context tag is generated thus operating system assigns a current context tag for the current process (See Fig. 2 and Column 1, lines 58-67 to Column 3, lines 1-17 for details regarding context information including process and thread identifiers)) and a secure branch prediction circuit configured to compare the current task identification with the previous branch task identification to generate a comparison result while the current task performs branch prediction of a branch instruction (Column 7, lines 8-25 and Column 8, lines 62-67 to Column 9, lines 1-9: wherein branch prediction structure compares the current context tag with a previous context tag stored in an entry of the branch predictor to generate a comparison result while the current process performs branch prediction of a branch instruction encountered by the current process (See Figs. 2-3)) and output a jump prediction message or a non-jump prediction message based on the comparison result. (Column 9, lines 10-40: wherein based on a matching comparison result a branch prediction message which causes fetch unit to fetch instructions and perform speculative execution based on accessed branch prediction information occurs. Wherein based on a non-matching comparison result a non-branch prediction message which causes normal sequential fetching occurs. (See Fig. 3) (Also note this limitation is interpreted similarly as indicated in paragraphs [0043-0045] of applicant’s specification which indicates that outputting the messages means that the prediction result of the branch instruction is taken or not taken))
Evers does not disclose a counter configured to generate a plurality of task identifications (TIDs) nor wherein the operating system writes the current task identification of the current task into a current ID buffer in response to a key owned by the current task being correct. Evers discloses context information controlled by an operating system including process context identifiers or thread identifiers, however Evers does not disclose using a counter to generate context identifiers or thread identifiers. Therefore, another reference is brought in for that teaching.
Luo discloses a counter configured to generate a plurality of task identifications (TIDs). ([0033]: wherein task identifiers are assigned using a counter)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor system of Evers which generates process and/or context identifiers to use a counter to generate process identifiers as taught in Luo. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (using a counter to generate process identifiers as taught in Luo) for another (generically generating process identifiers as taught in Evers) to yield predictable results (using a counter in a processor system to generate process identifiers) (MPEP 2143, Example B). Furthermore, it would have been obvious because using a counter to generate identifiers provides a simple and efficient technique to track tasks/processes in a processor.
The combination of Evers and Luo does not disclose wherein the operating system writes the current task identification of the current task into a current ID buffer in response to a key owned by the current task being correct.
Solomatnikov discloses wherein the operating system writes the current task identification of the current task into a current ID buffer ([0033 and 0082]: wherein operating system updates (writes) current context/process ID in register)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor which generates a current context identifier as taught in Evers to store a current context identifier in a dedicated register as disclosed in Solomatnikov. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (storing a current context ID in a dedicated register as taught in Solomatnikov) for another (generically storing current context ID as taught in Evers) to yield predictable results (using a dedicated register to store a current context ID) (MPEP 2143, Example B). It would have further been obvious because using a register to store information can be used for fast and efficient accessing in a processor.
The combination of Evers, Luo and Solomatnikov does not disclose writes the current task identification of the current task into a current ID buffer in response to a key owned by the current task being correct. The combination of references discloses writing a current task ID to a register; however, the combination does not disclose writing in response to a key owned by a current task being correct.
Wang discloses writes a task buffer in response to a key owned by the current task being correct. ([0020 and 0046]: wherein a global register is written by a current thread in response to an ID owned by the current thread matching the ID in the global resource (e.g. being a correct match) (See Fig. 5))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the writing or updating of a context ID register in the combination of Evers and Solomatnikov to be in response to a context owning a correct key as taught in Wang. It would have been obvious to one of ordinary skill in the art because writing a global register based upon checking a variable can prevent the register from being corrupted or modified by another context. (Wang [0022 and 0034]).
Claim 9 is similarly rejected on the same basis as claim 1 above as claim 9 is the method claim corresponding to the processor of claim 1 above.
Claim(s) 2-5, 7 and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Evers, Luo, Solomatnikov, Wang and further in view of Dashora, USPAT No. 12,099,844.
In regards to claim 2, the combination of Evers, Luo, Solomatnikov and Wang discloses The processor of claim 1 (see rejection of claim 1 above) wherein the secure branch prediction circuit is further configured to access a branch prediction structure to obtain a branch status and access a branch target buffer (BTB) to obtain an execution target address while the comparison result indicates that the current task identification is the same as the previous branch task identification. (Evers: Column 4, lines 58-63 and Column 9, lines 10-28: wherein a current process context tag and previous process context tag match a branch prediction structure is accessed to obtain a branch likelihood status and a branch target buffer is accessed to obtain a predicted destination address)
Evers does not explicitly disclose accessing a pattern history table (PHT) to obtain a branch status. Evers does disclose accessing a branch prediction structure that includes a saturating counter indicating a likelihood of branch outcomes, and a branch predictor including various known branch prediction structures. However, Evers has not explicitly disclosed a branch predictor including a pattern history table.
Dashora discloses accessing a pattern history table (PHT) to obtain a branch status. (Column 6, lines 26-35: wherein a pattern history table is accessed to obtain branch status (See Figs. 1 and 4A-5))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the branch predictor structure of Evers to include a pattern history table as the branch predictor disclosed in Dashora. It would have been obvious to one of ordinary skill in the art because using a pattern history table as disclosed in Dashora can be used to improve overall processor performance by reducing power consumption (Dashora: Column 3, lines 19-38). Furthermore, pattern history tables can improve branch prediction accuracy.
Claim 10 is similarly rejected on the same basis as claim 2 above as claim 10 is the method claim corresponding to the processor of claim 2 above.
In regards to claim 3, the combination of Evers, Luo, Solomatnikov, Wang and Dashora discloses The processor of claim 2 (see rejection of claim 2 above) wherein the secure branch prediction circuit is further configured to output the jump prediction message after accessing the branch status and the execution target address. (Evers: Column 9, lines 10-28: wherein the branch prediction structure outputs the branch prediction message after accessing branch status and predicted target address (See elements 325 and 335 of Fig. 3))
Claim 11 is similarly rejected on the same basis as claim 3 above as claim 11 is the method claim corresponding to the processor of claim 3 above.
In regards to claim 4, the combination of Evers, Luo, Solomatnikov, Wang and Dashora discloses The processor of claim 2 (see rejection of claim 2 above).
The combination of Evers, Luo, Solomatnikov, Wang and Dashora thus far does not disclose wherein the secure branch prediction circuit is further configured to flush the pattern history table and the branch target buffer while the comparison result indicates that the current task identification is different from the previous branch task identification. Evers does disclose flushing a branch prediction structure upon a context switch and denying access to a branch prediction structure when a comparison result indicates that the current task identification is different from the previous branch task identification. However, Evers does not disclose flushing the branch prediction structure based on a mismatch of the identifiers.
Solomatnikov discloses wherein the secure branch prediction circuit is further configured to flush the branch prediction structures while the comparison result indicates that the current task identification is different from the previous branch task identification ([0036, 0062 and 0065]: wherein branch prediction structure entries are discarded (e.g. flushed) while the comparison result of a process identifier is different from a previous identifier stored in the entry of the branch predictor structures)
It would been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the branch prediction circuitry of Evers to flush a branch prediction structure when comparison results of process identifiers differ as the branch prediction circuitry of Solomatnikov. It would have been obvious to one of ordinary skill in the art because constraining speculative execution by discarding branch prediction entries would eliminate or mitigate Spectre-class and side-channel attacks (Solomatnikov [0026-0027]).
Claim 12 is similarly rejected on the same basis as claim 4 above as claim 12 is the method claim corresponding to the processor of claim 4 above.
In regards to claim 5, the combination of Evers, Luo, Solomatnikov, Wang and Dashora discloses The processor of claim 4 (see rejection of claim 4 above). wherein the secure branch prediction circuit is further configured to output the non-jump prediction message after flushing the pattern history table and the branch target buffer. (Evers: Column 9, lines 29-40: wherein the branch prediction structure outputs the branch prediction message after denying access to the branch prediction structure (See elements 330 and 340 of Fig. 3) |Solomatnikov [0065-0066] (Note: combination of Dashora and Solomatnikov would disclose the flushing the pattern history and BTB. Thus, the combination of all references would disclose the above limitations))
Claim 13 is similarly rejected on the same basis as claim 5 above as claim 13 is the method claim corresponding to the processor of claim 5 above.
In regards to claim 7, the combination of Evers, Luo, Solomatnikov and Wang discloses The processor of claim 1 (see rejection of claim 1 above).
The combination of Evers, Luo, Solomatnikov and Wang does not disclose wherein the secure branch prediction circuit is designed utilizing a gshare-style 2-level predictor.
Dashora discloses branch prediction circuit is designed utilizing a gshare-style 2-level predictor. (See Fig. 5: wherein a gshare 2 level predictor is disclosed (See Column 15, lines 51-67))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the branch prediction structure of Evers to include a gshare predictor as disclosed in Dashora. It would have been obvious to one of ordinary skill in the art because a gshare branch predictor uses a dynamic prediction scheme which improves prediction accuracy by combining global branch history with a current branch address.
Claim 14 is similarly rejected on the same basis as claim 7 above as claim 14 is the method claim corresponding to the processor of claim 7 above.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Evers, Luo, Solomatnikov and Wang and further in view of Walker, PGPUB No. 2010/0057427.
In regards to claim 6, the combination of Evers, Luo, Solomatnikov and Wang discloses The processor of claim 1 (see rejection of claim 1 above).
The combination of Evers, Luo, Solomatnikov and Wang does not disclose wherein the processor is simulated by a cycle-accurate electronic system level (ESL) platform.
Walker discloses wherein the processor is simulated by a cycle-accurate electronic system level (ESL) platform. ([0010-0012]: wherein processor is simulated by a cycle accurate system model platform (See Fig. 1))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor system of Evers to be simulated using a cycle accurate model as the processor of Walker. It would have been obvious to one of ordinary skill in the art because using a cycle accurate model to simulate a processor provides precise timing analysis which would provide high accuracy performance.
Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Evers, Luo, Solomatnikov and Wang and further in view of Rollet, PGPUB No. 2023/0096461.
In regards to claim 8, the combination of Evers, Luo, Solomatnikov and Wang discloses The processor of claim 1 (see rejection of claim 1 above).
The combination of Evers, Luo, Solomatnikov and Wang does not disclose wherein the operating system is a FreeRTOS operating system.
Rollet discloses wherein the operating system is a FreeRTOS operating system. ([0054])
It would have been obvious to one of ordinary skill in before the effective filing date of the invention to modify the operating system of Evers to be a FreeRTOS as the operating system of Rollet. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using FreeRTOS operating system as taught in Rollet) for another (generic operating system as taught in Evers) to yield predictable results (using a FreeRTOS in a process system) for the benefit of using a real-time processing which provides consistency in scheduling and completing tasks (Rollet [0054]) (MPEP 2143, Example B).
Claim 15 is similarly rejected on the same basis as claim 8 above as claim 15 is the method claim corresponding to the processor of claim 8 above.
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Evers, USPAT No. 11,734,011 and further view of Wang, PGPUB No. 2014/0068232.
In regards to claim 9, Evers discloses A secure branch prediction method (See Fig. 3 and Column 8, lines 1-9) comprising: executing an operating system by a user core circuit (Column 4, lines 16-22 and Column 6, lines 12-16: wherein processor core of processing system executes operating system (element 110) (See Fig. 1)) to request the operating system to assign a current task identification to a current task while the current task is created (Column 6, lines 12-16 and Column 8, lines 9-37: wherein processor core, executing a current process, requests operating system assign context tag to a current process while the current process is created. Wherein operating system assigns context information from which context tag is generated thus operating system assigns a current context tag for the current process (See Fig. 2 and Column 1, lines 58-67 to Column 3, lines 1-17 for details regarding context information including process and thread identifiers)) comparing the current task identification with a previous branch task identification to generate a comparison result by a secure branch prediction circuit in response to the current task performing branch prediction of a branch instruction; and outputting a jump prediction message or a non-jump prediction message by the secure branch prediction circuit based on the comparison result. (Note: The following limitations are interpreted under broadest reasonable interpretation and are thus not required because they fall under contingent limitations that are not required to occur. The examiner interprets the claim such that the condition of the current task performing branch prediction of a branch instruction does not occur and thus the rest of the steps of the method claim are not required to occur.)
Evers does not disclose wherein the operating system write the current task identification of the current task into a current ID buffer in response to a key owned by the current task being correct. Evers discloses creating a current task identification, but does not disclose determining whether to write the identification to a register based on a key.
Wang discloses wherein the operating system write the current task identification of the current task into a current ID buffer in response to a key owned by the current task being correct. ([0020, 0040 and 0046]: wherein a global register is not written by a current thread in response to an ID owned by the current thread not matching the ID in the global resource (e.g. being an incorrect match) (See Fig. 5). The following limitations are interpreted under broadest reasonable interpretation (BRI) and thus the writing to a ID buffer is not required as a key owned by a current task is not correct))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Evers to include a protected register used to store global data as taught in Wang. It would have been obvious to one of ordinary skill in the art because using a global register based upon checking a variable can prevent the register from being corrupted or modified by another context and provide flexibility to the register (Wang [0022 and 0034]).
In regards to claim 10, the combination of Evers and Wang discloses The method of claim 9 (see rejection of claim 9 above) wherein the secure branch prediction circuit is further configured to access a pattern history table (PHT) to obtain a branch status and access a branch target buffer (BTB) to obtain an execution target address while the comparison result indicates that the current task identification is the same as the previous branch task identification. (The following limitations are interpreted under broadest reasonable interpretation (BRI) and are thus not required because they fall under contingent limitations that are not required to occur as an “accessing of a PHT and a BTB” are contingent upon a comparison occurring in claim 9 and thus are not required to occur because under BRI a comparison has not occurred in claim 9. In addition, claim 10 includes an additional contingent limitation stating “while” and thus the limitations of claim 10 are not required to occur unless the compared task identifications are the same)
In regards to claim 11, the combination of Evers and Wang discloses The method of claim 10(see rejection of claim 10 above) wherein the secure branch prediction circuit is further configured to output the jump prediction message after accessing the branch status and the execution target address. (The following limitations are interpreted under broadest reasonable interpretation (BRI) and are thus not required because they fall under contingent limitations that are not required to occur as an “accessing of a PHT and a BTB” are contingent upon a comparison occurring in claim 9 and thus are not required to occur because under BRI the limitations of claims 9-10 have not occurred)
In regards to claim 12, the combination of Evers and Wang discloses The method of claim 10 (see rejection of claim 10 above) wherein the secure branch prediction circuit is further configured to flush the pattern history table and the branch target buffer while the comparison result indicates that the current task identification is different from the previous branch task identification. (The following limitations are interpreted under broadest reasonable interpretation (BRI) and are thus not required because they fall under contingent limitations that are not required to occur as an “flushing of a PHT and a BTB” are contingent upon a comparison occurring in claim 9 and thus are not required to occur because under BRI a comparison has not occurred in claim 9. In addition, claim 12 includes an additional contingent limitation stating “while” and thus the limitations of claim 12 are not required to occur unless the compared task identifications are different)
In regards to claim 13, the combination of Evers and Wang discloses The method of claim 12 (see rejection of claim 12 above) wherein the secure branch prediction circuit is further configured to output the non-jump prediction message after flushing the pattern history table and the branch target buffer. (The following limitations are interpreted under broadest reasonable interpretation (BRI) and are thus not required because they fall under contingent limitations that are not required to occur as an “flushing of a PHT and a BTB” are contingent upon a comparison occurring in claim 9 and thus are not required to occur because under BRI the limitations of claims 9-10 and 12 have not occurred)
Response to Arguments
Applicant’s arguments, see pages 16-20 of the remarks filed on 3/5/2026, with respect to the respective rejection(s) of claim(s) 1 and 9 under Evers or Evers and Luo in view of 35 USC 102 and/or 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 103 under Evers, Luo, Solomatnikov and Wang for claims 1 and 9; as well as Evers and Wang for the contingent claim interpretation of the method claim 9.
Claims 2-8 and 10-15 are dependent upon one of independent claims 1 and 9 and thus remain rejected at least based upon their respective dependencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Peeters, PGPUB No. 2018/0063100 for teaching comparing keys of thread identifiers stored in thread ID register to see if thread has access to data in a secure memory block
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183
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