DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/23/2026 has been entered.
Response to Arguments
Applicant's arguments filed 04/23/2026 have been fully considered but they are not persuasive.
Examiner respectfully disagrees with the applicant’s argument that “Park has not been shown by the Office Action to disclose at least the features a third transistor connected to a gate of the first transistor and a second terminal of the first transistor, a gate of the third transistor being directly connected to a second gate line, a fourth transistor connected to the gate of the first transistor and a first initialization voltage line, a gate of the fourth transistor being connected to a third gate line, and a fifth transistor connected to the second transistor and a reference voltage line, a gate of the fifth transistor being directly connected to the second gate line, and wherein the fifth transistor comprises a first sub-transistor, as recited in amended claim 1” (pages 9-10 of applicant’s remarks).
Claim 1 does not recite “a gate of the fifth transistor being directly connected to the second gate line”. Claim 1 recites “a gate of the fifth transistor being connected to the second gate line.”
Therefore, Park et al. teaches a third transistor (transistor T52 of pixel P2 in Fig. 8, transistor T53 of pixel P3 in Fig. 8) connected to a gate of the first transistor(transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8: note that the claim does not recite “directly” connected. All the elements in Fig. 8 are connected to each other) and a second terminal of the first transistor (transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8), a gate of the third transistor (transistor T52 of pixel P2 in Fig. 8, transistor T53 of pixel P3 in Fig. 8) being directly connected to a second gate line (EM line in Fig. 8); a fourth transistor (transistor T12 of pixel P2 in Fig. 8, transistor T13 of pixel P3 in Fig. 8) connected to the gate of the first transistor (transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8) and a first initialization voltage line (ELVDD line in Fig. 8), a gate of the fourth transistor (transistor T12 of pixel P2 in Fig. 8, transistor T13 of pixel P3 in Fig. 8) being connected to a third gate line (GW line in Fig. 8); a fifth transistor (transistor T42 of pixel P2 in Fig. 8, transistor T43 of pixel P3 in Fig. 8) connected to the second transistor (transistor T22 of pixel P2 in Fig. 8, transistor T23 of pixel P3 in Fig. 8) and a reference voltage line (horizontal VINTL line in Fig. 8), a gate of the fifth transistor (transistor T42 of pixel P2 in Fig. 8, transistor T43 of pixel P3 in Fig. 8) being connected to the second gate line (EM line in Fig. 8: note that the claim does not recite “directly” connected. All of the elements in Fig. 8 are connected to each other), wherein the fifth transistor comprises a first sub-transistor (transistor T42 of pixel P2 in Fig. 8, transistor T43 of pixel P3 in Fig. 8),” as claimed. Furthermore, Examiner respectfully disagrees with the applicant’s argument that “nowhere has Park been shown to teach or suggest that the EM line (alleged "third gate line") in FIG. 8 is a "gate line" as recited in claim 1.” Applicant argues that ”Park has not been shown to disclose a correlation between the emission control line EML and "the first control line GWL applying the first gate control signal GW, and the second control line GIL applying the second gate control signal G1."
Park et al. teaches “a gate of the third transistor (transistor T52 of pixel P2 in Fig. 8, transistor T53 of pixel P3 in Fig. 8) being directly connected to a second gate line (EM line in Fig. 8)” and “a gate of the fifth transistor (transistor T42 of pixel P2 in Fig. 8, transistor T43 of pixel P3 in Fig. 8) being connected to the second gate line (EM line in Fig. 8: note that the claim does not recite a gate of the fifth transistor being “directly” connected to the second gate line. All of the elements in Fig. 8 are connected to each other),” as recited in claim 1.
Furthermore, In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a correlation between the emission control line EML and the first control line GWL applying the first gate control signal GW, and the second control line GIL applying the second gate control signal G1) are not recited in the claim.
Park et al. teaches all of the recited features of claim 1.
Regarding claim 11, Examiner respectfully disagrees with the applicant’s argument that “No has not been shown by the Office Action to disclose at least the features “a third transistor connected to a gate of the first transistor and a second terminal of the first transistor, a gate of the third transistor being connected to a second gate line" and "a fifth transistor connected to the second transistor and a reference voltage line, a gate of the fifth transistor being directly connected to the second gate line", as recited in amended claim 11.”
No et al. teaches a third transistor (T11 in Fig. 15) connected to a gate of the first transistor (T1
in Fig. 15) and a second terminal of the first transistor (T1 in Fig. 15; note the claim does not recite
“directly” connected. All of the elements in Fig. 15 are connected to each other), a gate of the third
transistor (T11 in Fig. 15) being connected to a second gate line (GL2p in Fig. 15; note the claim does not
recite “directly” connected. All of the elements in Fig. 15 are connected to each other); a fifth transistor
(T4 in Fig. 15) connected to the second transistor (T2 in Fig. 15) and a reference voltage line (VILp line in
Fig. 15), a gate of the fifth transistor (T4 in Fig. 15) being directly connected to the second gate line
(GL2p in Fig. 15),” as claimed.
No et al. teaches all of the recited features of claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2016/0064411 A1).
As to claim 1, Park et al. teaches a display apparatus (Abstract: display apparatus) comprising: a plurality of pixels (Abstract: pixels; Fig. 8, pixels P2, P3), wherein each of the plurality of pixels (Abstract: pixels; Fig. 8, pixels P2, P3) comprises: a first transistor (transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8); a second transistor (transistor T22 of pixel P2 in Fig. 8, transistor T23 of pixel P3 in Fig. 8) connected to a data line (DL_G line in Fig. 8 directly connected to transistor T22 of pixel P2 in Fig. 8, DL_B line in Fig. 8 directly connected to transistor T23 of pixel P3 in Fig. 8), a gate of the second transistor (transistor T22 of pixel P2 in Fig. 8, transistor T23 of pixel P3 in Fig. 8) being connected to a first gate line (GW line in Fig. 8) ; a third transistor (transistor T52 of pixel P2 in Fig. 8, transistor T53 of pixel P3 in Fig. 8) connected to a gate of the first transistor(transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8: note that the claim does not recite “directly” connected. All the elements in Fig. 8 are connected to each other) and a second terminal of the first transistor (transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8), a gate of the third transistor (transistor T52 of pixel P2 in Fig. 8, transistor T53 of pixel P3 in Fig. 8) being directly connected to a second gate line (EM line in Fig. 8); a fourth transistor (transistor T12 of pixel P2 in Fig. 8, transistor T13 of pixel P3 in Fig. 8) connected to the gate of the first transistor (transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8) and a first initialization voltage line (ELVDD line in Fig. 8), a gate of the fourth transistor (transistor T12 of pixel P2 in Fig. 8, transistor T13 of pixel P3 in Fig. 8) being connected to a third gate line (GW line in Fig. 8); a fifth transistor (transistor T42 of pixel P2 in Fig. 8, transistor T43 of pixel P3 in Fig. 8) connected to the second transistor (transistor T22 of pixel P2 in Fig. 8, transistor T23 of pixel P3 in Fig. 8) and a reference voltage line (horizontal VINTL line in Fig. 8), a gate of the fifth transistor (transistor T42 of pixel P2 in Fig. 8, transistor T43 of pixel P3 in Fig. 8) being connected to the second gate line (EM line in Fig. 8: note that the claim does not recite “directly” connected. All of the elements in Fig. 8 are connected to each other), wherein the fifth transistor comprises a first sub-transistor (transistor T42 of pixel P2 in Fig. 8, transistor T43 of pixel P3 in Fig. 8); and a capacitor (capacitor C2 of pixel P2 in Fig. 8; capacitor C3 of pixel P3 in Fig. 8) connected to the gate of the first transistor (transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8) and the second transistor (transistor T22 of pixel P2 in Fig. 8, transistor T23 of pixel P3 in Fig. 8), wherein the plurality of pixels comprise a first pixel (P3 in Fig. 8) and a second pixel (P2 in Fig. 8) adjacent to the first pixel (P3 in Fig. 8),
wherein the fifth transistor comprised in the first pixel and the fifth transistor comprised in the second pixel further comprise a second sub-transistor (transistor T40 in Fig. 8) shared by the first pixel (P3 in Fig. 8) and the second pixel (P2 in Fig. 8), and wherein the second sub-transistor (transistor T40 in Fig. 8) shared by the first pixel (P3 in Fig. 8) and the second pixel (P2 in Fig. 8): is connected in series with the first sub-transistor of the fifth transistor of the first pixel (transistor T43 of pixel P3 in Fig. 8) and is closer to the reference voltage line (horizontal VINTL line in Fig. 8; transistor T40 is directly connected to horizontal VINTL line) than the first sub-transistor of the fifth transistor of the first pixel (transistor T43 of pixel P3 in Fig. 8); and is connected in series with the first sub-transistor of the fifth transistor of the second pixel (transistor T42 of pixel P2 in Fig. 8) and is closer to the reference voltage line (horizontal VINTL line in Fig. 8; transistor T40 is directly connected to horizontal VINTL line) than the first sub-transistor of the fifth transistor of the second pixel (transistor T42 of pixel P2 in Fig. 8). As to claim 2, Park et al. teaches the display apparatus of claim 1, wherein the first pixel (P3 in Fig. 8) and the second pixel (P2 in Fig. 8) share a contact area where the second sub-transistor (transistor T40 in Fig. 8) is connected to the reference voltage line (horizontal VINTL line in Fig. 8).
As to claim 3, Park et al. teaches the display apparatus of claim 1, wherein the second sub-transistor (transistor T40 in Fig. 8) is arranged at a boundary between the first pixel (P3 in Fig. 8) and the second pixel (P2 in Fig. 8), and wherein an arrangement of transistors of the first pixel(P3 in Fig. 8), other than the second sub-transistor (transistor T40 in Fig. 8), and an arrangement of transistors of the second pixel (P2 in Fig. 8), other than the second sub-transistor(transistor T40 in Fig. 8), are symmetric to each other with respect to the boundary between the first pixel (P3 in Fig. 8) and the second pixel (P2 in Fig. 8). As to claim 10, Park et al. teaches the display apparatus of claim 1, wherein each of the plurality of pixels further comprises:an eighth transistor (transistor T62 of pixel P2, transistor T63 of pixel P3, Fig. 8) connected to the second terminal of the first transistor (transistor T32 of pixel P2 in Fig. 8, transistor T33 of pixel P3 in Fig. 8)and a light-emitting element (OLED2 of pixel P2, OLED3 of pixel P3); anda ninth transistor (transistor T72 of pixel P2, transistor T73 of pixel P3, Fig. 8) connected to the light-emitting element (OLED2 of pixel P2, OLED3 of pixel P3) and a second initialization voltage line (vertical VINT line in Fig. 8), wherein the plurality of pixels further comprise a third pixel (pixel P1 in Fig. 8) adjacent to the second pixel (pixel P2 in Fig. 8), and wherein the second pixel (pixel P2 in Fig. 8) and the third pixel (pixel P1 in Fig. 8) share a contact area where the ninth transistor of the second pixel (transistor T72 of pixel P2) and the ninth transistor of the third pixel (transistor T71 of pixel P1) are connected to the second initialization voltage line (Fig. 8 shows transistor T72 of pixel P2 and transistor T71 of pixel P1 are connected to vertical voltage line VINT through contact area where transistor T71 of pixel P1 and transistor T72 of pixel P2 are directly connected to VINTL line).
Claim(s) 11-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by No et al. (US 2023/0368736 A1).
As to claim 11, No et al. teaches a display apparatus ([0056]: display apparatus) comprising:
a plurality of pixels ([0060]: pixels; [0184]: i-th pixel (PXi) and the i+1-th pixel (PXi+1),
wherein each of the plurality of pixels ([0060]: pixels; [0184]: i-th pixel (PXi) and the i+1-th pixel (PXi+1))
comprises:
a first transistor (T1 in Fig. 15);
a second transistor (T2 in Fig. 15) connected to a data line (DATA line in Fig. 15), a gate of the
second transistor (T2 in Fig. 15) being connected to a first gate line (GL1i in Fig. 15; [0181]; note the
claim does not recite “directly” connected. All of the elements in Fig. 15 are connected to each other);
a third transistor (T11 in Fig. 15) connected to a gate of the first transistor (T1 in Fig. 15) and a
second terminal of the first transistor (T1 in Fig. 15; note the claim does not recite “directly” connected.
All of the elements in Fig. 15 are connected to each other), a gate of the third transistor (T11 in Fig. 15)
being connected to a second gate line (GL2p in Fig. 15; note the claim does not recite “directly”
connected. All of the elements in Fig. 15 are connected to each other);
a fourth transistor (T9 in Fig. 15) connected to the gate of the first transistor (T1 in Fig. 15; note
the claim does not recite “directly” connected. All of the elements in Fig. 15 are connected to each
other) and a first initialization voltage line (VREF line in Fig. 15), a gate of the fourth transistor (T9 in Fig.
15) being connected to a third gate line (GL3p line in Fig. 15);
a fifth transistor (T4 in Fig. 15) connected to the second transistor (T2 in Fig. 15) and a reference
voltage line (VILp line in Fig. 15), a gate of the fifth transistor (T4 in Fig. 15) being directly connected to
the second gate line (GL2p in Fig. 15); and
a capacitor (C1 in Fig. 15) connected to the gate of the first transistor (T1 in Fig. 15) and the
second transistor (T2 in Fig. 15),
wherein the plurality of pixels comprise a first pixel (PXi in Fig. 15) and a second pixel (PXi+1 in
Fig. 15) adjacent to the first pixel (PXi in Fig. 15), wherein the first pixel and the second pixel share:
a sixth transistor (T5 in Fig. 15; [0184]: i-th pixel (PXi) and the i+1-th pixel (PXi+1) share the
transistor T5) connected to a bias voltage line (ELVDD line in Fig. 15), a gate of the sixth transistor being
connected to a fourth gate line (GL4p in Fig. 15; [0184]), and
wherein the sixth transistor (T5 in Fig. 15) is shared by the first pixel and the second pixel
([0184]: i-th pixel (PXi) and the i+1-th pixel (PXi+1) share the transistor T5) and is connected to a first
terminal of the first transistor (T1 in Fig. 15) of the first pixel (PXi in Fig. 15) and a first terminal of the
first transistor (T1 in Fig. 15) of the second pixel (PXi+1 in Fig. 15).
As to claim 12, No et al. teaches the display apparatus of claim 11, wherein the sixth transistor
(T5 in Fig. 15) shared by the first pixel (PXi in Fig. 15) and the second pixel (PXi+1 in Fig. 15) is arranged
at a boundary between the first pixel (PXi in Fig. 15) and the second pixel (PXi+1 in Fig. 15), and wherein
an arrangement of transistors of the first pixel (PXi in Fig. 15), other than the sixth transistor (T5 in Fig.
15), and an arrangement of transistors of the second pixel (PXi+1 in Fig. 15), other than the sixth
transistor (T5 in Fig. 15), are symmetric to each other with respect to the boundary between the first
pixel (PXi in Fig. 15) and the second pixel (PXi+1 in Fig. 15; [0180]: i-th pixel PXi and the (i+1)-th pixel
(PXi+1) have symmetrical structure).
As to claim 13, No et al. teaches the display apparatus of claim 11, wherein the first pixel (PXi in
Fig. 15) and the second pixel (PXi+1 in Fig. 15) share a seventh transistor (T8 in Fig. 15; [0184]:
i-th pixel (PXi) and the i+1-th pixel (PXi+1) share the transistor T8) connected to a driving voltage line
(ELVSS line in Fig. 15; note the claim does not recite “directly” connected. All of the elements in Fig. 15
are connected to each other), and wherein the seventh transistor (T8 in Fig. 15) shared by the first pixel
(PXi in Fig. 15) and the second pixel (PXi+1 in Fig. 15) is connected to the first terminal of the first
transistor (T1 in Fig. 15) of the first pixel (PXi in Fig. 15) and the first terminal of the first transistor (T1 in
Fig. 15) of the second pixel ((PXi+1) in Fig. 15).
As to claim 14, No et al. teaches the display apparatus of claim 13, wherein the seventh
transistor (T8 in Fig. 15) shared by the first pixel (PXi in Fig. 15) and the second pixel (PXi+1 in Fig. 15;
[0184]) is arranged at a boundary between the first pixel (PXi in Fig. 15) and the second pixel (PXi+1 in
Fig. 15), and wherein an arrangement of transistors of the first pixel (PXi in Fig. 15), other than the
seventh transistor (T8 in Fig. 15), and an arrangement of transistors of the second pixel (PXi+1 in Fig. 15),
other than the seventh transistor (T8 in Fig. 15), are symmetric to each other with respect to the
boundary between the first pixel (PXi in Fig. 15) and the second pixel (PXi+1 in Fig. 15; [0180]: i-th pixel
PXi and the (i+1)-th pixel (PXi+1) have symmetrical structure).
As to claim 15, No et al. teaches the display apparatus of claim 11, wherein the first pixel (PXi in
Fig. 15) and the second pixel (PXi+1 in Fig. 15) share a contact area where the fifth transistor (T4 in Fig.
15) of the first pixel (PXi in Fig. 15) and the fifth transistor (T4 in Fig. 15) of the second pixel (PXi+1 in Fig.
15) are connected to the reference voltage line (VILp line in Fig. 15).
Allowable Subject Matter
Claims 4-9 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
Prosecution Insights