DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 1 – 8, 12, 13, 16, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al. (2021/0383737; hereinafter Byun) and Shi et al. (2019/0057664; hereinafter Shi) in view of In et al. (2016/0140903; hereinafter In; this combination of references hereinafter referred to as BSI).
Regarding claim 1, Byun discloses a gate driver [0002] comprising:
a pull-up circuit (Figure 7: Comprising TN8) which outputs a first clock signal (Comprising CLK3) as a gate output signal (Comprising SN1) in response to a voltage of a first control node (Comprising NN1);
a pull-down circuit (Comprising TN9) which pulls down the gate output signal (Comprising SN1) to a power voltage (Comprising VSS) in response to a voltage of a second control node (Comprising NN2);
a first control circuit (Comprising TN7) which applies the first clock signal (Comprising CLK3) to the first control node (Comprising NN1) in response to the voltage of the second control node (Comprising NN2);
a second control circuit (Comprising 250) which controls a voltage of the first control node (Comprising NN1) in response to a voltage of a third control node (Comprising NN6) and a second clock signal (Comprising CLK2); and
a third control circuit (Comprising TP1) which applies a masking enable signal (Comprising OS2) to the third control node (Comprising NN6).
Byun does not explicitly disclose the driver wherein masking enable transmission is in response to the first clock signal.
In the same field of endeavor, Shi discloses a GOA driving circuit [0008] whose node Q(N) (Figure 6) pulled low by circuitry (Comprising 370) operating on the basis of the first clock signal (Comprising CK; [0046]; see also, applied at one of source and drain of T3). Per the aforementioned passage, this among measures implemented to prevent the sudden introduction of a large current.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the driver of Byun to be modified wherein masking enable transmission is in response to the first clock signal, in view of the teaching of Shi, to prevent the introduction of an abrupt and large current.
Byun in view of Shi does not explicitly disclose the driver wherein the masking enable signal is different from a vertical start signal, and wherein the masking enable signal is different from the power voltage.
In the same field of endeavor, In discloses a display device scanline driver [0003] wherein the masking enable (Figure 4: N4 pulled low by transmission of CLK1 by 113; [0042]) signal is different from a vertical start signal ([0043]: SCAN_IN = SSP), and wherein the masking enable signal is different from the power voltage (e.g. VGH). This is among measures implemented to reduce the amount of circuitry in the display edge [0038].
It would be obvious to one having ordinary skill in the art at the time of invention for the driver of Byun to be modified wherein the masking enable signal is different from a vertical start signal, and wherein the masking enable signal is different from the power voltage, in view of the teaching of In, to reduce the amount of circuitry in the display edge.
Regarding claim 2, BSI discloses the gate driver of claim 1. Byun discloses the driver wherein the pull-up circuit comprises a ninth transistor (Figure 7: Comprising TN8) including a control electrode (Comprising gate of TN8) connected to the first control node (Comprising NN1), a first electrode (Comprising one of source, drain of TN8) which receives the first clock signal (Comprising CLK3) and a second electrode (Comprising other of source, drain of TN8) connected to a gate output terminal (Comprising SN1).
Regarding claim 3, BSI discloses the gate driver of claim 1. Byun discloses the driver wherein the pull-down circuit comprises a tenth transistor (Figure 7: Comprising TN9) including a control electrode (Comprising gate of TN9) connected to the second control node (Comprising NN2), a first electrode (Comprising one of source, drain of TN9) connected to a gate output terminal (Comprising SN1) and a second electrode (Comprising other one of source, drain of TN9) which receives the power voltage (Comprising VSS).
Regarding claim 4, BSI discloses the gate driver of claim 1. Byun discloses the driver wherein the first control circuit comprises an eleventh transistor (Figure 7: Comprising TN7) including a control electrode (Comprising gate of TN7) connected to the second control node (Comprising NN2), a first electrode (Comprising one of source, drain of TN7) which receives the first clock signal (Comprising CLK3) and a second electrode (Comprising other one of source, drain of TN7) connected to the first control node (Comprising NN1).
Regarding claim 5, BSI discloses the gate driver of claim 1. Byun discloses the driver wherein the second control circuit comprises: a sixth transistor (Figure 7: Comprising TN5) including a control electrode (Comprising gate of TN5) connected to the third control node (Comprising NN6), a first electrode (Comprising one of source, drain of TN5) connected to a first node (Comprising NN7) and a second electrode (Comprising other one of source, drain of TN5) which receives the second clock signal (Comprising CLK2); and a seventh transistor (Comprising TN6) including a control electrode (Comprising gate of TN6) which receives the second clock signal (Comprising CLK2), a first electrode (Comprising one of source, drain of TN6) connected to the first node (Comprising NN7) and a second electrode (Comprising other one of source, drain of TN6) connected to the first control node (Comprising NN1).
Regarding claim 6, BSI discloses the gate driver of claim 5. Byun discloses the driver wherein the second control circuit further comprises a second capacitor (Figure 7: Comprising CN2) including a first electrode (Comprising one of two capacitor plate electrodes of CN2) connected to the third control node (Comprising NN6) and a second electrode (Comprising other one of two capacitor plate electrodes of CN2) connected to the first node (Comprising NN7).
Regarding claim 7, BSI discloses the gate driver of claim 1.
Byun does not expressly state the driver being provided wherein the third control circuit comprises a third transistor including a control electrode which receives the first clock signal, a first electrode which receives the masking enable signal and a second electrode connected to a second node.
In the same field of endeavor, Shi discloses a GOA driving circuit [0008] wherein the third control circuit comprises a third transistor (Figure 6: Comprising T16) including a control electrode (Comprising gate of T16) which receives the first clock signal (Comprising CK), a first electrode (Comprising one of source, drain of T16) which receives the masking enable signal (Comprising Vss) and a second electrode (Comprising other one of source, drain of T16) connected to a second node (Comprising S{N}). This among measures implemented to prevent the sudden introduction of a large current [0046].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the driver of Byun to be modified wherein the third control circuit comprises a third transistor including a control electrode which receives the first clock signal, a first electrode which receives the masking enable signal and a second electrode connected to a second node, to prevent the introduction of an abrupt and large current.
Regarding claim 8, BSI discloses the gate driver of claim 7. Byun discloses the driver wherein the gate driver further comprises a fourth transistor (Figure 7: Comprising TN4) including a control electrode (Comprising gate of TN4) which receives the power voltage (Comprising VSS), a first electrode (Comprising one of source, drain of TN4) connected to the second node (Comprising NN3) and a second electrode (Comprising other one of source, drain of TN4) connected to the third control node (Comprising NN6).
Regarding claim 12, BSI discloses the gate driver of claim 1. Byun discloses the driver wherein the gate driver further comprises a fifth control circuit (Figure 7: Comprising 240) which controls the voltage of the second control node (Comprising NN2) using the second clock signal (Comprising CLK2) in response to the voltage of the second control node (Comprising NN2).
Regarding claim 13, BSI discloses the gate driver of claim 12. Byun discloses the driver wherein the fifth control circuit comprises: a second transistor (Figure 7: Comprising TN2) including a control electrode (Comprising gate of TN2) connected to the second control node (Comprising NN2), a first electrode (Comprising one of source, drain of TN2) connected to a fourth node (Comprising NN5) and a second electrode (Comprising other one of source, drain of TN2) which receives the second clock signal (Comprising CLK2); and a third capacitor (Comprising CN1) including a first electrode (Comprising one of two capacitor plate electrodes of CN1) connected to the second control node (Comprising NN2) and a second electrode (Comprising other one of two capacitor plate electrodes of CN1) connected to the fourth node (Comprising NN5).
Regarding claim 16, BSI discloses the gate driver of claim 1. Byun discloses the driver wherein the gate driver further comprises a first capacitor (Figure 7: Comprising CN3) including a first electrode (Comprising one of two capacitor plate electrodes of CN3) which receives the first clock signal (Comprising CLK3) and a second electrode (Comprising other one of two capacitor plate electrodes of CN3) connected to the first control node (Comprising NN1).
Regarding claim 21, Byun discloses an electronic apparatus comprising a display apparatus (Figure 1) comprising:
a display panel (Comprising 100) including a pixel (Comprising PX);
a gate driver (Comprising at least one of 200, 400) which outputs a gate output signal ([0057], [0064]) to the pixel (Comprising PX), the gate driver comprising:
a pull-up circuit (Figure 7: Comprising TN8) which outputs a first clock signal (Comprising CLK3) as the gate output signal (Comprising SN1) in response to a voltage of a first control node (Comprising NN1);
a pull-down circuit (Comprising TN9) which pulls down the gate output signal (Comprising SN1) to a power voltage (Comprising VSS) in response to a voltage of a second control node (Comprising NN2);
a first control circuit (Comprising TN7) which applies the first clock signal (Comprising CLK3) to the first control node (Comprising NN1) in response to the voltage of the second control node (Comprising NN2);
a second control circuit (Comprising 250) which controls a voltage of the first control node (Comprising NN1) in response to a voltage of a third control node (Comprising NN6) and a second clock signal (Comprising CLK2); and
a third control circuit (Comprising TP1) which applies a masking enable signal (Comprising OS2) to the third control node (Comprising NN6); and
a data driver (Figure 1: Comprising 300) which outputs a data voltage [0063] to the pixel (Comprising PX).
Byun does not explicitly disclose the apparatus wherein masking enable transmission is in response to the first clock signal.
In the same field of endeavor, Shi discloses a GOA driving circuit [0008] whose node Q(N) (Figure 6) pulled low by circuitry (Comprising 370) operating on the basis of the first clock signal (Comprising CK; [0046]; see also, applied at one of source and drain of T3). Per the aforementioned passage, this among measures implemented to prevent the sudden introduction of a large current.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Byun to be modified wherein masking enable transmission is in response to the first clock signal, in view of the teaching of Shi, to prevent the introduction of an abrupt and large current.
Byun in view of Shi does not explicitly disclose the apparatus wherein the masking enable signal is different from a vertical start signal, and wherein the masking enable signal is different from the power voltage.
In the same field of endeavor, In discloses a display device scanline driver [0003] wherein the masking enable (Figure 4: N4 pulled low by transmission of CLK1 by 113; [0042]) signal is different from a vertical start signal ([0043]: SCAN_IN = SSP), and wherein the masking enable signal is different from the power voltage (e.g. VGH). This is among measures implemented to reduce the amount of circuitry in the display edge [0038].
It would be obvious to one having ordinary skill in the art at the time of invention for the apparatus of Byun to be modified wherein the masking enable signal is different from a vertical start signal, and wherein the masking enable signal is different from the power voltage, in view of the teaching of In, to reduce the amount of circuitry in the display edge.
ii. Claims 9, 10, 14, 17, 23 are rejected under 35 U.S.C. 103 as being unpatentable over BSI, as respectively applied to claims 1, 21 above, and further in view of Song et al. (2022/0328008; hereinafter Song; this combination of references hereinafter referred to as BSIS).
Regarding claim 9, BSI discloses the gate driver of claim 1.
BSI does not explicitly disclose the driver wherein the gate driver further comprises a fourth control circuit which controls the voltage of the third control node using the first clock signal in response to the voltage of the second control node.
However, Song discloses a method of driving [0002] scan stages comprising masking circuits [0015] wherein the gate driver further comprises a fourth control circuit (Figure 11: Comprising M4–2) which controls the voltage of the third control node (Comprising N4) using the first clock signal (Comprising CLK3) in response to the voltage of the second control node (Comprising N1). This is among measures implemented to prevent a brightness difference between pixel rows [0243].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the driver of Byun to be modified wherein the gate driver further comprises a fourth control circuit which controls the voltage of the third control node using the first clock signal in response to the voltage of the second control node, in view of the teaching of Song, to resolve the brightness difference between pixel rows.
Regarding claim 10, BSIS discloses the gate driver of claim 9.
Byun does not explicitly disclose the driver wherein the gate driver further comprises a short preventing circuit which prevents a short between the first clock signal and the voltage of the third control node.
However, Song discloses a method of driving [0002] scan stages comprising masking circuits [0015] wherein the gate driver further comprises a short preventing circuit (Figure 11: Comprising M4–1) which prevents a short between the first clock signal (Comprising CLK3) and the voltage of the third control node (Comprising N4). This is among measures implemented to prevent a brightness difference between pixel rows [0243].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the driver of Byun to be modified wherein the gate driver further comprises a short preventing circuit which prevents a short between the first clock signal and the voltage of the third control node, in view of the teaching of Song, to resolve the brightness difference between pixel rows.
Regarding claim 14, BSI discloses the gate driver of claim 1.
BSI does not explicitly disclose the driver wherein the gate driver further comprises an input circuit which applies an input signal to the second control node in response to the first clock signal.
However, Song discloses a method of driving [0002] scan stages comprising masking circuits [0015] wherein the gate driver further comprises an input circuit (Figure 11: Comprising M1, M12) which applies an input signal (Comprising FLM_GC) to the second control node (Comprising N1) in response to the first clock signal (Comprising CLK3). This is among measures implemented to prevent a brightness difference between pixel rows [0243].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the driver of Byun to be modified wherein the gate driver further comprises an input circuit which applies an input signal to the second control node in response to the first clock signal, in view of the teaching of Song, to resolve the brightness difference between pixel rows.
Regarding claim 17, BSI discloses the gate driver of claim 1.
BSI does not explicitly disclose the driver wherein in a state in which the masking enable signal has an inactive level, a gate output terminal outputs the gate output signal, and wherein in a state in which the masking enable signal has an active pulse, the gate output terminal does not output the gate output signal.
However, Song discloses a method of driving [0002] scan stages comprising masking circuits [0015] capable of masking a scan signal’s (Figure 13A: Comprising e.g. GC2) output as a carry signal (Comprising CR2) per the degree of overlap with the pulse of masking signals (Comprising MSK3, MSK4), rectifying (Figure 13B) the lesser degree of overlap between masking (Comprising MSK–P) and scan (Comprising GC2) signals, by which a residual carry signal (Comprising RS1) are output. This is among measures implemented to prevent a brightness difference between pixel rows [0243].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the driver of Byun to be modified wherein in a state in which the masking enable signal has an inactive level, a gate output terminal outputs the gate output signal, and wherein in a state in which the masking enable signal has an active pulse, the gate output terminal does not output the gate output signal, in view of the teaching of Song, to resolve the brightness difference between pixel rows.
Electronic apparatus claim 23 is rejected as reciting limitations similar to those recited in gate driver claim 17.
Allowable Subject Matter
Claims 11, 15, 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11, BSIS discloses the gate driver of claim 10.
The cited prior art fails to singularly or collectively disclose the driver wherein the fourth control circuit comprises a fifth transistor including a control electrode connected to the second control node, a first electrode which receives the first clock signal and a second electrode connected to a third node, and wherein the short preventing circuit comprises a twelfth transistor including a control electrode which receives the masking enable signal, a first electrode connected to the third node and a second electrode connected to a second node.
Thus, claim 11 is objected to.
Regarding claim 15, BSIS discloses the gate driver of claim 14.
The cited prior art fails to singularly or collectively disclose the driver wherein the input circuit comprises: a first transistor including a control electrode which receives the first clock signal, a first electrode which receives the input signal and a second electrode connected to a fifth node; and an eighth transistor including a control electrode which receives the power voltage, a first electrode connected to the fifth node and a second electrode connected to the second control node.
Thus, claim 15 is objected to.
Regarding claim 22, BSI discloses the electronic apparatus of claim 21.
The cited prior art fails to singularly or collectively disclose the driver wherein the gate driver further comprises: a fourth control circuit which controls the voltage of the third control node using the first clock signal in response to the voltage of the second control node; and a short preventing circuit which prevents a short between the first clock signal and the voltage of the third control node, wherein the fourth control circuit comprises a fifth transistor including a control electrode connected to the second control node, a first electrode which receives the first clock signal and a second electrode connected to a third node, and wherein the short preventing circuit comprises a twelfth transistor including a control electrode which receives the masking enable signal, a first electrode connected to the third node and a second electrode connected to a second node.
Thus, claim 22 is objected to.
--
Claims 18 – 20 are allowed.
The following is an examiner’s statement of reasons for allowance: the claimed invention is directed toward a gate driver comprising first through twelfth transistors, wherein a first clock is received by each among a control electrode of the first transistor, a control electrode of the third transistor, a first electrode of the fifth transistor, a first electrode of the ninth transistor and a first electrode of the eleventh transistor, wherein a masking enable signal is received by each of a first electrode of the third transistor and a control electrode of the twelfth transistor.
What follows a mapping of claim 18 to the aforementioned reference Byun et al. (2021/0383737).
Regarding claim 18, Byun discloses a gate driver comprising:
a second transistor (Comprising TN2) including a control electrode (Comprising gate electrode of TN2) connected to a second control node (Comprising NN2), a first electrode (Comprising one of source, drain of TN2) connected to a fourth node (Comprising NN5) and a second electrode (Comprising other one of source, drain of TN2) which receives a second clock signal (Receiving CLK2);
a fourth transistor (Comprising TN4) including a control electrode (Comprising gate electrode of TN4) which receives a power voltage (Comprising VSS), a first electrode (Comprising one of source, drain of TN4) connected to the second node (Comprising NN3) and a second electrode (Comprising other one of source, drain of TN4) connected to a third control node (Comprising NN6);
a sixth transistor (Comprising TN5) including a control electrode (Comprising gate electrode of TN5) connected to the third control node (Comprising NN6), a first electrode (Comprising one of source, drain of TN5) connected to a first node (Comprising NN7) and a second electrode (Comprising other one of source, drain of TN5) which receives a second clock signal (Comprising CLK2);
a seventh transistor (Comprising TN6) including a control electrode (Comprising gate electrode of TN6) which receives the second clock signal (Comprising CLK2), a first electrode (Comprising one of source, drain of TN6) connected to the first node (Comprising NN7) and a second electrode (Comprising other one of source, drain of TN6) connected to a first control node (Comprising NN1);
an eighth transistor (Comprising TN1) including a control electrode (Comprising gate electrode of TN1) which receives the power voltage (Comprising VSS), a first electrode (Comprising one of source, drain of TN1) connected to the fifth node (Comprising NN4) and a second electrode (Comprising other one of source, drain of TN1) connected to the second control node (Comprising NN2);
a ninth transistor (Comprising TN8) including a control electrode (Comprising gate electrode of TN8) connected to the first control node (Comprising NN1), a first electrode (Comprising one of source, drain of TN8) which receives the first clock signal (Comprising CLK3) and a second electrode (Comprising other one of source, drain of TN8) connected to a gate output terminal (Comprising SN1);
a tenth transistor (Comprising TN9) including a control electrode (Comprising gate electrode of TN9) connected to the second control node (Comprising NN2), a first electrode (Comprising one of source, drain of TN9) connected to the gate output terminal (Comprising SN1) and a second electrode (Comprising other one of source, drain of TN9) which receives the power voltage (Comprising VSS);
an eleventh transistor (Comprising TN7) including a control electrode (Comprising gate electrode of TN7) connected to the second control node (Comprising NN2), a first electrode (Comprising one of source, drain of TN7) which receives the first clock signal (Comprising CLK3) and a second electrode (Comprising other one of source, drain of TN7) connected to the first control node (Comprising NN1).
The cited prior art fails to singularly or collectively disclose the gate driver further comprising a first transistor including a control electrode which receives a first clock signal, a first electrode which receives an input signal and a second electrode connected to a fifth node; a third transistor including a control electrode which receives the first clock signal, a first electrode which receives a masking enable signal and a second electrode connected to a second node; a fifth transistor including a control electrode connected to the second control node, a first electrode which receives the first clock signal and a second electrode connected to a third node; a twelfth transistor including a control electrode which receives the masking enable signal, a first electrode connected to the third node and a second electrode connected to the second node.
Thus, claim 18 is allowed.
Claims 19, 20 depend from and inherit limitations of claim 18.
Thus, claims 19, 20 are allowed.
--
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Inquiries
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Aaron Midkiff whose telephone number is (571)270-5875. The examiner can normally be reached Monday - Friday, 8:00am - 4:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at (571)272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621