DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Natarajan et al. (Patent 12517657), hereinafter as Natarajan, in view of Mattausch et al. (PGPUB 20120188811), hereinafter as Mattausch.
Regarding claim 1, Natarajan teaches a memory system comprising: a memory device (Fig 1, 108) configured to store data for in-memory searching;
a memory controller (Fig 1, 102) configured with logic to (i) program the memory device, according to one or more programming voltages, to store storage data (Fig 1-2, inherent functionality), (ii) provide one or more search voltages to the memory device in dependence on input data (Fig 2, 221 and 222, input vectors) and (iii) determine a level of similarity between the stored storage data and the input data
configuration circuitry including logic to determine a base threshold voltage (Vt) according to which the memory controller (i) programs the memory device using the one or more programming voltages to set one or more threshold voltages (the examiner is taking note, the step (i) is well known in the field) and (ii) provides the one or more search voltages (Fig 2 and col 6, line 3-64),
wherein the base threshold voltage (Vt) is determined between the stored logical value represented by the storage data and the input logical value represented by the input data (col 6, line 44-52),
But not expressly an output current represents an Euclidean distance between to vectors,
Mattausch teaches an output current represents an Euclidean distance between to vectors ([0233]).
Since Mattausch and Natarajan are both from the same field of semiconductor memory device, the purpose disclosed by Mattausch would have been recognized in the pertinent art of Natarajan.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use an output current as in Mattausch into the device of Natarajan for the purpose of quantify the a comparison result between two sets of data.
Regarding claim 13, Natarajan teaches the memory device is a multi-level content addressable memory (MCAM) (col 14, line 30-32).
Regarding claim 18, Natarajan teaches a memory device comprising: memory cells configured to store data for in-memory searching (Fig 1, memorys); and
a memory controller (Fig 1, processor) configured with logic to:
program the memory device to store storage data according to one or more threshold voltages set in dependence on a base threshold voltage (Vt),
provide one or more search voltages to the memory device in dependence on input data, the one or more search voltages being set in dependence on a base threshold voltage (Vt) (Fig 1-2, inherent functionality of memory cell), and
determine a level of similarity between the stored storage data and the input data according to a Euclidean distance (col 6, line 44-52) between a stored logical value represented by the stored storage data and an input logical value represented by the input data (Fig 2, 221 and 222, input vectors),
wherein the base threshold voltage (Vt) is determined, between the stored logical value represented by the stored storage data and the input logical value represented by the input data (col 6, line 44-52);
Mattausch teaches an output current represents an Euclidean distance between to vectors ([0233]).
The reason for combining the references used in rejection of claim 1 applies.
Claim(s) 2-4, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Natarajan and Mattausch, in view of Koezuka et al. (PGPUB 20180254352), hereinafter as Koezuka.
Regarding claim 2, Natarajan and Mattausch teach a memory system as in rejection of claim 1,
But not expressly how to determine a threshold voltage of a memory cell,
Koezuka teaches that a threshold voltage (Vt) is determined in dependence on an ideal base threshold voltage Vt that is calculated by extrapolating a line with respect to known or determined characteristics of the memory device that are represented by a √Id vs gate voltage (Vg) curve, where Id is a drain current provided by a memory device in response to the gate voltage (Vg) ([0075]).
Since Natarajan and Koezuka are both from the same field of semiconductor memory device, the purpose disclosed by Koezuka would have been recognized in the pertinent art of Natarajan.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the methodology used in Koezuka into the device of Natarajan for the purpose of setting value of threshold voltage of the memory cell.
Regarding claim 3, Natarajan teaches the logic to determine the base threshold voltage (Vt) includes: calculating a partial derivative curve from the known or determined characteristics of the memory device that are represented by the Id vs gate voltage (Vg) curve; and identifying, as the ideal base threshold voltage Vt, a value of the gate voltage (Vg) determined in dependence on a peak point of the calculated partial derivative curve and a line that is tangent to a determined point on the Id vs gate voltage (Vg) curve that corresponds to the peak point, wherein the base threshold voltage (Vt) is set in dependence on the calculated ideal base threshold voltage Vt ([0076]).
Regarding claim 4, Natarajan teaches the logic to determine the base threshold voltage (Vt) further includes: determining a Vg peak value, which is a voltage that aligns with the peak point of the calculated partial derivative curve; determining the point on the Id vs gate voltage (Vg) curve that aligns with the determined Vg peak value; calculating the line that is tangent to the determined point on the Id vs gate voltage (Vg) curve to have a slope defined by the peak point of the calculated partial derivative curve; and determining the ideal base threshold voltage Vt value to correspond to a point on the calculated line where Id = 0 ([0076]).
Regarding claim 19, argument used in rejection of claim 2 applies.
Regarding claim 20, argument used in rejection of claim 3 applies.
Claim(s) 5, 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Natarajan, Mattausch and Koezuka, in view of Singidi et al. (Patent 10366763), hereinafter as Singidi.
Regarding claim 5, Natarajan, Mattausch and Koezuka teach a memory system,
but not expressly use a base line threshold to be used,
Singidi teaches the base threshold voltage (Vt) is determined in dependence on an extracted base threshold voltage Vt that is calculated by applying the ideal base threshold voltage Vt to a group of memory cells within the memory device (Claim 1).
Since Natarajan and Singidi are both from the same field of semiconductor memory device, the purpose disclosed by Singidi would have been recognized in the pertinent art of Natarajan.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the methodology used in Singidi into the device of Natarajan for the purpose of setting value of threshold voltage of the memory cell.
Regarding claim 7, Singidi teaches the memory controller is configured with logic to store one logical value of n logical values as the stored logical value represented by the stored data in each cell of the memory device, n being an integer greater than zero (col 2).
Regarding claim 8, Singidi teaches n has a value ranging from 1 to 8 (col 2, TLC cell).
Regarding claim 9, Singidi teaches to set a ∆V voltage value according to which the base threshold voltage (Vt) is adjusted to store different logical values of the n logical values (Fig 5).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Natarajan, Mattausch, Koezuka, and Singidi, in view of Ajika et al. (PGPUB 20100283099), hereinafter as Ajika.
Regarding claim 6, Natarajan, Mattausch, Koezuka, and Singidi teach a memory system,
but not expressly using fixed current to determine threshold,
Ajika teaches determining an actual median drain current Id at the calculated ideal base threshold voltage Vt for a group of memory cells within the memory device and defining the median drain current Id as current Ith; and determining the extracted base threshold voltage Vt from the known drain current Id vs gate voltage (Vg) curve as a voltage on the known drain current Id vs gate voltage (Vg) curve that corresponds to the current Ith, such that the extracted base threshold voltage Vt is an adjusted version of the ideal base threshold voltage Vt that is adjusted in dependence on actual varying performance among the group of memory cells ([0267]).
Since Natarajan and Ajika are both from the same field of semiconductor memory device, the purpose disclosed by Ajika would have been recognized in the pertinent art of Natarajan.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the methodology used in Ajika into the device of Natarajan for the purpose of setting value of threshold voltage of the memory cell.
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Natarajan and Mattausch, in view of Lee (PGPUB 20140347933), hereinafter as Lee.
Regarding claim 14, Natarajan and Mattausch teach a memory system as in rejection of claim 1,
But not expressly a 2d NOR flash memory,
Lee teaches the memory device is a 2D NOR flash memory, wherein a pair of rows in a particular column in the 2D NOR flash memory is used to store data, wherein wordlines connected to the pair of rows in the particular column in the 2D NOR flash memory (Fig 5F) are used to input data which is compared to the stored data, and wherein one or more data words can be stored in a column of the 2D NOR flash memory.
Since Natarajan and Lee are both from the same field of semiconductor memory device, the purpose disclosed by Lee would have been recognized in the pertinent art of Natarajan.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use arrangement as in Lee into the device of Natarajan for the purpose of enabling a CAM memory.
Regarding claim 15, Lee teaches the 2D NOR flash memory is configured at two-transistor (2T) NOR flash memory and one transistor of each 2T transistor pair is configured to enable or disable searching on a particular row of transistors (Fig 5A).
Regarding claim 16, Lee teaches the 2D NOR flash memory is configured as split-gate NOR flash memory and one gate of each transistor is configured to enable or disable searching on a particular row of transistors (Fig 5A).
Regarding claim 17, the examiner is taking note that it is known in the field that the memory device is a 3D NOR flash memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
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