DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1 -19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 10505579) in view of Sibrai et al. (US 20050152092).
PNG
media_image1.png
422
328
media_image1.png
Greyscale
PNG
media_image2.png
211
404
media_image2.png
Greyscale
PNG
media_image3.png
248
622
media_image3.png
Greyscale
With respect to claim 1, figures 4, 11 and 12 of Jo et al. (US 10505579) produce a method of reducing switching time of a radio frequency (RF) switch, the RF switch comprising: a switch stack (fig. 4; 110) including a plurality of transistors (M1-M3) arranged in a stack configuration; a plurality of gate resistors (RG1-RG3), each gate resistor being connected to a gate terminal of a corresponding transistor of the plurality of transistors, the plurality of gate resistors being tied together at a first terminal (i.e. VG10, VG1, VG2 or VG3 through the delay circuit) of the RF switch; a capacitor (inside delay circuit labelled CV1 of fig. 11 or 12) coupling the first terminal to ground; and a series resistor (RDS1 in series with RDS2 and RDS3) connecting a second terminal (between M1 and M2) of the RF switch (figures 4, 11 and 12) to the first terminal (at M1) but fails to disclose the method comprising when transitioning from an ON state to an OFF state or from the OFF state to the ON state: in a first step, bypassing the plurality of gate resistors, and in a second step, delayed from the first step, bypassing the capacitor.
PNG
media_image4.png
180
373
media_image4.png
Greyscale
Figure 3 of Sabrai et al. (US 20050152092) discloses the details of a variable capacitor that can be used as the variable capacitor in Jo.
It would have been obvious at the would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the variable capacitor of Sibrai in the circuit of Jo for the purpose of achieving better linearity, a high Q factor and more fully describing the invention.
The resulting would produce a method wherein in a first step a plurality of gate resistors would be bypassed (i.e. R3 to R7 or RG1-RG3 for example) and in a second step delayed from the first step bypassing the capacitor (i.e. one of C8-CN could be selected depending on the desired resulting resistance alternatively, the capacitor can also be bypassed depending on the selection i.e. VG1, VG2 or VG3)
With respect to claim 2, the combination above produces the method of claim 1, wherein the bypassing the gate resistors (i.e. RG1-RG3 for example by selection) is performed using a plurality of gate switches (M1-M3 ), and wherein each gate switch is coupled across a gate resistor (RG1-RG3) of the plurality of gate resistors.
With respect to claim 3, the combination above produces the method of claim 1, further comprising, in the second step, bypassing the series resistor (i.e. (RDS1 in series with RDS2 and RDS3 by selection ).
With respect to claim 4, the combination above produces the method of claim 1, wherein the bypassing of the gate resistors (RG1-RG3) and capacitor (C1-Cn) is controlled by control pulses (i.e. Vcii) and wherein the widths of the control pulses are selected based on a switching time of the switch stack (selection based on switching time and switch stack are inherent in the selection of the desired result).
With respect to claim 5, the combination above produces the method of claim 2, wherein the gate switches (M1-M3) are controlled with a control pulse (VG1-VG3) applied to gate terminals of the plurality of gate switches.
With respect to claim 6, the combination above produces a method for operating a radio frequency (RF) switch, the RF switch comprising a switch stack (fig. 4; 110) including a plurality of transistors (M1-M3) arranged in a stack configuration; a plurality of gate resistors (RG1-RG3),, each gate resistor being connected to a gate terminal of a corresponding transistor of the plurality of transistors, the plurality of gate resistors being tied together at a first terminal (i.e. VG10, VG1, VG2 or VG3 through the delay circuit) of the RF switch; a capacitor (inside delay circuit labelled CV1 of fig. 11 or 12) coupling the first terminal to ground; and a first switch (here T1-Tn are “coupled” across the capacitors (C1-Cn) where fig. 3 is variable capacitor in fig. 12) coupled across the capacitor (fig. 3 of Sabrai), the method comprising: transitioning the switch stack between ON and OFF states, while selectively bypassing the capacitor during the transition (transition based on the selection for desired outcome).
With respect to claim 7, the combination above produces the method of claim 6, wherein the bypassing of the capacitor is performed using the first switch (i.e. T1-Tn) controlled by a control pulse (i.e Vcii).
With respect to claim 8, the combination above produces the method of claim 6, further comprising bypassing a series resistor (by selection for desired result of the resistor) connected to a second terminal (i.e. one of VG10, VG1, VG2 or VG3 through the delay circuit) of the RF switch during the transition of the switch stack.
With respect to claim 9, the combination above produces the method of claim 8, wherein the bypassing of the series resistor occurs after a delay from bypassing the capacitor (selection of desired value of the capacitor can occur before the desired selection of the appropriate series resistor).
With respect to claim 10, the combination produces the method of claim 6, wherein the first switch (one of M1-M3) is controlled with a control pulse applied at a gate terminal of the first switch (applied from VG10-VG3).
With respect to claim 11, the combination produces a radio frequency (RF) switch comprising: a switch stack (fig. 4; 110)including a plurality of transistors (M1-M3) arranged in a stack configuration; a plurality of gate resistors (RG1-RG3), each gate resistor being connected to a gate terminal of a corresponding transistor of the plurality of transistors, the plurality of gate resistors being tied together at a first terminal (i.e. one of VG10, VG1, VG2 or VG3 through the delay circuit) of the RF switch; a first capacitor (inside delay circuit labelled CV1 of fig. 11 or 12, here CV is replaced by variable capacitor of fig. 3 of Sabrai) coupling the first terminal to ground; a first switch (i.e. one of T1-TN) coupled across the capacitor; a second capacitor inside delay circuit labelled CV2 of fig. 11 or 12, here CV is replaced by variable capacitor of fig. 3 of Sabrai) configured to couple the first terminal to ground, and a second switch (i.e. one of T1-Tn) configured to control the coupling of the second capacitor.
With respect to claim 12, the combination produces the RF switch of claim 11, further comprising a third switch (one of M1-M3 i.e. M3) coupled across a series resistor (one of RG1_-RG3 i.e. RG3) connecting a second terminal of the RF switch to the first terminal (i.e. one of VG10, VG1, VG2 or VG3 through the delay circuit), the third switch being configured to bypass the series resistor during transitions of the RF switch (based on switch selection).
With respect to claim 13, the combination produces the RF switch of claim 11, wherein the first and second capacitors (i.e. aforementioned CV1 and CV2) are selectively coupled to the first terminal via a control signal (selected from CVii) applied to the second switch (via intervening circuits in 140).
With respect to claim 14, the combination produces the RF switch of claim 11, wherein during the transition of the RF switch, the second capacitor is switched in, and the first capacitor is switched out (Here, the desired switching in and out is capable of being produced based on desired results and seen as obvious expedient).
With respect to claim 15, the combination produces the RF switch of claim 12, wherein the bypassing of the series resistor (One of (RDS1 in series with RDS2 and RDS3 by selection ) is controlled by a separate control signal (VG1-VG3 i.e. VG3) applied to the third switch (One of M1-M3 i.e. M3).
With respect to claim 16, the combination produces the RF switch of claim 11, wherein the second switch is a FET (One of the switches M1-M3 are FETs and the second switch i.e. M2 would read on this claim)
With respect to claim 17, the combination produces the RF switch of claim 11, further comprising a switch driver (i.e. 130) configured to control the first, second, and third switches in sequence during transitions of the RF switch. (Note: here, the sequence selection would be obvious for the desired result).
With respect to claim 18, the combination produces the RF switch of claim 11, wherein the coupling of the second capacitor occurs only after the first capacitor has been bypassed (It is deemed obvious expedient to couple the second capacitor as such to achieve desired results and would be seen as obvious).
With respect to claim 19, the combination produces the RF switch of claim 12, wherein the third switch (one of M1-M3 i.e. M3) is controlled with a control pulse (i.e. one of VG10-VG3) applied at a gate terminal of the third switch (i.e if M3 is selected as the third switch then VG3 controls the gate terminal.) .
Allowable Subject Matter
Claim 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 20, the prior art fails to suggest or disclose the RF switch of claim 11, wherein the first and the second capacitor are pre-charged with opposite polarity voltages.
Here, per figure 11, the capacitors are both charged with the same precharge being ground and no compelling reason is present to charge them with opposite precharge values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F(8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAREEM E ALMO/Examiner, Art Unit 2849
Prosecution Insights