DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive.
Applicant argues that the claimed invention requires determining “two distinct fixed LLR values” and applying those values uniformly across all elements of the noisy codeword, relying heavily on the embodiment described in paragraphs 60-71 of the specification.
The claims, however, do not recite:
a lookup table;
fixed LLR values;
uniform values throughout the codeword;
identical values assigned to every zero bit or every one bit; or
the particular embodiment illustrated in Applicant’s example.
Instead, claim 1 merely recites:
determining… a first LLR value indicative of a bit being zero-valued and a second LLR value indicative of the bit being one-valued; and
generating an LLR sequence by applying the first LLR value and the second LLR value to each element of the noisy codeword.
Under the broadest reasonable interpretation consistent with the specification, the claims merely require two LLR values that are used in constructing an LLR sequence. And the claims do not exclude implementations in which those values are derived from or combined with other reliability information.
Accordingly, Applicant’s arguments rely upon unclaimed limitations and therefore are not commensurate in scope with the claims.
Applicant argues that Fossorier computes a per-bit reliability metric rather than two LLR values. The Examiner respectfully disagrees because the rejection does not rely upon Fossorier for literal disclosure of Applicant’s preferred implementation. Rather, Fossorier teaches assigning reliability information to bits for use during LDPC decoding. A log-likelihood ratio is itself a reliability metric expressing confidence regarding whether a received bit corresponds to a logical “0” or logical “1.” Although Fossorier denotes the reliability quantity by E_n rather than “LLR,” the reference expressly teaches computing a signed reliability metric whose sign indicates the preferred bit value and whose magnitude reflects confidence in that decision.
Accordingly, Fossorier teaches the same functional use of reliability information recited in the claims and the nomenclature employed by the reference does not patentably distinguish the claims.
Applicant repeatedly argues that Fossorier computes N reliability metrics while the claims require only two values. However, the rejection does not equate the entire vector of reliability metrics with the claimed first and second LLR values. Rather, Zhang teaches estimating global statistical properties of the received codeword (ones count, checksum, asymmetric ratio), while Fossorier teaches representing decoding reliability using soft information. Therefore, it would have been obvious to utilize Zhang’s estimated statistics to initialize or generate decoder reliability information expressed in the conventional LLR domain as taught by Fossorier before performing decoding. Besides, nothing in claim 1 excludes additional reliability calculations after the claimed determining step, nor does it prohibit generating an LLR sequence containing additional position-dependent information. Therefore Applicant’s distinction between “two values” and “N values” is not commensurate with the claim language.
Applicant argues that Fossorier’s weighting factor α is obtained through simulation rather than from the ones count and checksum. However, this argument attacks the references individually and the rejection is based upon the combination of Zhang and Fossorier. Zhang expressly teaches determining an asymmetric ratio from estimated codeword statistics and Fossorier teaches incorporating reliability weighting into LDPC bit-flipping decoding. The rejection proposes using Zhang’s estimated statistical information as the source of reliability weighting during the initialization of the decoder. Besides, a rejection under 35 U.S.C. 103 does not require bodily incorporation of one reference into another nor substitution of identical variables. Instead, the issue is whether the combined teachings would have suggested using estimated channel statistics to generate decoder reliability values before decoding.
Applicant has not shown why such a modification would have been beyond the ordinary level of skill.
Applicant argues that one of ordinary skill would not have used Zhang’s asymmetric ratio to modify Fossorier’s weighting factor. This argument is likewise unpersuasive because both references address improving LDPC decoding performance by improving the quality of reliability information used during decoding. For instance, Zhang teaches estimating global channel asymmetry from the received codeword. And Fossorier teaches improving decoding performance through improved reliability weighting. Because both references seek improved decoding accuracy through more representative reliability metrics, one of ordinary skill would have recognized that Zhang’s estimated statistical information could beneficially inform the reliability initialization employed by Fossorier. The proposed combination merely substitutes one known source of reliability information for another to obtain the predictable benefit of improved decoder initialization and such substitution is well within ordinary skill.
Applicant argues that Fossorier performs modified weighted bit flipping rather than the claimed hard decoding. This argument is not persuasive. Modified weighted bit-flipping is a hard-decision LDPC decoding algorithm. The algorithm begins with hard decisions and iteratively flips bits based upon reliability information. Accordingly, Fossorier expressly teaches performing a hard decoding operation using reliability metrics to generate a decoded candidate codeword, as relied upon in the rejection.
Accordingly, the rejection of claims 1-20 under 35 U.S.C. § 103 is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0403634 A1) and further in view of Zhang and Fossorier (“A Modified Weighted Bit-Flipping Decoding of Low-Density Parity-Check Codes,” IEEE Communications Letters, Vol. 8, No. 3, March 2004).
Claim 1: Zhang et al. teach a method for improving a performance of a decoder in a memory device (e.g., Abstract, ¶0001, ¶0026, ¶0029]), comprising:
receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code (e.g. Zhang et al. teach that data is stored in a memory block as LDPC codewords. Upon a data read command, voltage measurements are taken to determine bits, resulting in a “noisy” version of the stored (transmitted) codeword due to errors. See Abstract, ¶0028]. LDPC codes are explicitly used , ¶0028]);
determining, based on the noisy codeword, a ones count and a checksum (e.g. Zhang et al. explicitly teach: determining a first count “C₁” of bits that are determined as a one (the “ones count”), and computing a checksum “S” of the bits that are determined based on the voltage measurements. See ¶0031, Fig. 6, elements 604, 606. The checksum is directly related to the syndrome of the codeword - ¶0064]).
Zhang et al. also teach estimating a first number of errors E₀₁ (0→1) and a second number E₁₀ (1→0) based on C₁ (ones count) and a checksum-derived flip bit count E (e.g. Fig. 6, elements 612, 614). Zhang et al further teach that these estimated error counts (E₀₁ and E₁₀) can be used as input to a decoding procedure (e.g., ¶0008]) and can be “converted to soft information for use in the soft decoding procedure” (e.g., ¶0061]). The ratio of these numbers (E₀₁/E₁₀) constitutes the claimed “asymmetric ratio” (e.g., ¶0028]).
While Zhang et al provide the critical mechanism for deriving the asymmetric error ratio from simple channel measurements, it does not explicitly claim or detail the specific step of converting that information into log-likelihood ratios (LLRs) and then performing a hard decoding operation on that LLR sequence. Zhang et al discuss using the information for soft decoding or for adjusting read parameters, but do not expressly disclose the combination of generating LLRs from the estimated statistics and feeding those LLRs into a hard decoder (e.g., ¶0061]).
However, Zhang and Fossorier teach a Modified Weighted Bit-Flipping (MWBF) decoding algorithm that explicitly combines check-based information with bit-based reliability information to improve decoding performance (e.g. Abstract, Section III). The algorithm generates a reliability metric E_n for each bit using Equation (4): E_n = Σ (2s_m - 1)|y|_min - α·|y_n|. This metric incorporates both: check-based information derived from the syndrome (the checksum) (Σ (2s_m - 1)|y|_min), and bit-based intrinsic information (α·|y_n|), which is a function of the bit's received magnitude and thus its probability of being 0 or 1 (e.g., Section III).
This reliability metric is functionally equivalent to the claimed LLR values—it provides a measure of confidence that a bit is 0 or 1. A PHOSITA would recognize that such reliability metrics are routinely expressed as LLRs in the field . The MWBF algorithm then performs hard decoding (bit-flipping) using these metrics to generate a candidate decoded codeword (e.g. Section III, Step 3).
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to combine the teaching of Zhang et al with the one taught by Zhang and Fossorier for the following reasons: Zhang and Fossorier explicitly state that “for different codes with different column weights…the weight of the bit messages |y_n| should not be the same” and introduces a weighting factor α that can be optimized (e.g. Section III). Thus, a PHOSITA would have been motivated to use the asymmetric ratio derived from Zhang et al. to inform this weighting factor or otherwise refine the reliability metric.
Claim 2: Zhang et al and Zhang and Fossorier teach the method of claim 1, wherein determining the checksum comprises: determining a syndrome of the noisy codeword (e.g., Zhang et al. ¶0064; Zhang & Fossorier Equation (2) (syndrome component s_m)).
Claim 3: Zhang et al and Zhang and Fossorier teach the method of claim 1, wherein determining the checksum comprises: determining a partial checksum based a product of the noisy codeword and a submatrix of a parity-check matrix of the LDPC code (e.g., Zhang et al. ¶0064 (checksum S = d × H); Zhang & Fossorier Section II (syndrome calculation)).
Claim 4: Zhang et al and Zhang and Fossorier teach the method of claim 1, wherein determining the asymmetric ratio comprises: determining a difference between (a) the ones count of the noisy codeword and (b) a length of the transmitted codeword divided by two (e.g., Zhang et al. ¶¶0031, 0069-0070 (C₁, C₀, E calculations inherently involve such differences)).
Claim 5: Zhang et al and Zhang and Fossorier teach the method of claim 1, wherein determining the asymmetric ratio comprises: determining a difference between (a) the ones count of the noisy codeword and (b) a ones count of the transmitted codeword (e.g., Zhang et al. ¶¶0031, 0069-0070 (E₀₁ and E₁₀ calculations inherently compare to true values) ).
Claim 6: Zhang et al and Zhang and Fossorier teach the method of claim 5, but fail to teach that the ones count of the transmitted codeword is stored in one or more punctured information bits of the transmitted codeword. However, Zhang et al. teach storing data in a memory as codewords, and upon reading, determining a ones count (C₁) from the noisy codeword (e.g., Fig. 6, element 606). Zhang et al further teach estimating errors by comparing the observed ones count to what would be expected from the transmitted (stored) codeword (e.g., ¶¶0069–0070, equations for E₀₁ and E₁₀). This necessarily implies knowledge of characteristics of the transmitted codeword, including its ones count. Zhang et al. also teach that “information bits” are encoded into codewords (e.g., ¶0034, Fig. 1). Thus, a PHOSITA would understand that puncturing, the practice of not transmitting certain bits to increase code rate, is a common technique in LDPC coding. Punctured bits are typically known to the decoder and can carry information about the transmitted codeword. Furthermore, Zhang and Fossorier teach the fundamental structure of LDPC codes, including that a transmitted codeword is generated from information bits (e.g., Section I). A PHOSITA would understand that puncturing is a well-known technique in LDPC coding where some coded bits are not transmitted, and the decoder must account for these punctured bits during decoding. Information about the transmitted codeword (such as its weight or ones count) can be embedded in these punctured bits without affecting transmission efficiency.
Therefore, it would have been obvious to a PHOSITA to store the ones count of the transmitted codeword in punctured information bits because storing the true ones count in punctured bits would provide the decoder with accurate information needed for the error estimation taught by Zhang et al. (e.g., ¶¶0069–007). A PHOSITA seeking to implement Zhang's error estimation method would naturally look for ways to make the true ones count available to the decoder, and using punctured bits for this purpose is an obvious and efficient solution.
Claim 7: Zhang et al and Zhang and Fossorier teach the method of claim 1, but fail to teach that the transmitted codeword is generated by LDPC encoding a scrambled data sequence. However, the concept of scrambling data before encoding is a well-known technique in digital communications and storage systems. Scrambling is used to randomize data patterns, improve timing recovery, and avoid long runs of identical bits that can cause problems in storage media. Therefore, it would have been obvious to a PHOSITA to scramble the data sequence before LDPC encoding because scrambling improves the performance of LDPC codes by ensuring that the input to the encoder has good statistical properties (e.g., balanced ones and zeros), which can improve decoder performance. This is particularly important in memory devices where data patterns can affect cell wear and error rates.
Claim 8: Zhang et al and Zhang and Fossorier teach the method of claim 1, but fail to teach that the transmitted codeword is generated by scrambling an LDPC encoded data sequence. However, scrambling after encoding (or at the physical layer) is also a well-known technique in communication systems to shape the spectrum of the transmitted signal and ensure DC balance. Therefore, it would have been obvious to a PHOSITA to scramble the LDPC encoded data sequence because physical layer scrambling helps with timing recovery, avoids long runs of identical symbols, and can improve the performance of the read channel in storage devices (e.g., Zhang, ¶0054, discussing voltage thresholds and read parameters that could benefit from balanced data).
Claim 9: Zhang et al and Zhang and Fossorier teach the method of claim 1, wherein determining the first LLR value and the second LLR value comprises: retrieving the first LLR value and the second LLR value from a lookup table by using the ones count and the checksum to index into the lookup table (e.g. Zhang’s error counts can index predetermined LLRs. See ¶0027]).
Claim 10: Zhang et al and Zhang and Fossorier teach the method of claim 1, wherein the memory device comprises a quad-level cell (QLC) (e.g., Zhang et al. ¶0053 (explicitly discusses QLC NAND flash)).
Claims 11-20 are directed to system and computer-readable medium embodiments that correspond to the method claims of claims 1-10. Accordingly, claims 11-20 are rejected on same grounds as claims 1-10.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 7/17/2026
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