Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 20 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) and under 35 U.S.C. 120 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/02/2024 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 9, 11 – 14, and 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fai et al., U.S. Publication 2013/0007348 (herein Fai), in view of Hoel et al., U.S. Publication 2023/0138906 (herein Hoel).
Regarding claim 1, Fai teaches: A circuit device comprising: memory access circuitry (figure 1B); a set of registers coupled to the memory access circuitry (figure 1B, element 176); and control circuitry coupled to the memory access circuitry (figure 1B, element 172) and configured to: cause the memory access circuitry to: retrieve a set of parameter data from a memory (paragraph 0036, 0037); and store the set of parameter data in the set of registers (figure 4, element 410; paragraph 0036, 0037); and provide the set of parameter data from the set of registers to a set of system elements (figure 4, element 410; paragraph 0036, 0037). Fai does not explicitly teach: direct memory access (DMA) circuitry.
Hoel teaches: direct memory access (DMA) circuitry (paragraph 0025).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Fai: a set of registers coupled to the memory access circuitry, and control circuitry coupled to the memory access circuitry; with the teaching of Hoel: direct memory access (DMA) circuitry for the purpose of memory control (paragraph 0014). Memory access circuitry is well-known in the art (paragraph 0033 – 0043). Direct memory access (DMA) is a well-known design choice in the art (paragraph 0014). One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result.
Regarding claim 2, Fai and Hoel teach the limitations of the parent claim. Fai does not explicitly teach: the control circuitry is configured to cause the DMA circuitry to retrieve the set of parameter data using a block transfer.
Hoel teaches: DMA circuitry to retrieve the set of parameter data using a block transfer (paragraph 0025, 0032). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 3, Fai and Hoel teach the limitations of the parent claim. Fai teaches: the set of system elements includes a random access memory (figure 1B, element 180a). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 4, Fai and Hoel teach the limitations of the parent claim. Fai teaches: the set of system elements is a first set of system elements (figure 1B, element 180a); Fai does not explicitly teach: control circuitry is configured to: detect an initialization state of a second set of system elements; and perform the causing of the DMA circuitry to retrieve the set of parameter data from the memory based on the initialization state.
Hoel teaches: the control circuitry is configured to: detect an initialization state of a second set of system elements (paragraph 0025, 0026); and perform the causing of the DMA circuitry to retrieve the set of parameter data from the memory based on the initialization state (paragraph 0025, 0026). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 9, Fai and Hoel teach the limitations of the parent claim. Fai teaches: a processor core configured to execute boot code after the providing of the set of parameter data to the set of system elements (paragraph 0020). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 11, Fai and Hoel teach the limitations of the parent claim. Fai teaches: the memory coupled to the DMA circuitry, wherein the memory includes flash memory (figure 1B, element 180a). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 12, Fai teaches: A circuit device comprising: a non-volatile memory configured to store a set of parameters associated with a set of system elements (figure 1B, element 176); memory access circuitry coupled to the non-volatile memory (figure 1B, element 172); a set of registers coupled to the memory access circuitry, wherein the memory access circuitry is configured to copy the set of parameters from the non-volatile memory to the set of registers (paragraph 0036, 0037); and circuitry coupled to the set of registers and configured to provide the set of parameters from the set of registers to the set of system elements (figure 4, element 410). Fai does not explicitly teach: direct memory access (DMA) circuitry.
Hoel teaches: direct memory access (DMA) circuitry (paragraph 0025). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 13, Fai and Hoel teach the limitations of the parent claim. Fai does not explicitly teach: the DMA circuitry is configured to copy the set of parameters from the non-volatile memory to the set of registers using a block transfer.
Hoel teaches: the DMA circuitry is configured to copy the set of parameters from the non-volatile memory to the set of registers using a block transfer (paragraph 0025, 0032). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 14, Fai and Hoel teach the limitations of the parent claim. Fai teaches: the set of system elements is a first set of system elements (figure 1B, element 180a). Fai does not explicitly teach: control circuitry is configured to: detect an initialization state of a second set of system elements; and perform the causing of the DMA circuitry to retrieve the set of parameter data from the memory based on the initialization state.
Hoel teaches: the control circuitry is configured to: detect an initialization state of a second set of system elements (paragraph 0025, 0026); and perform the causing of the DMA circuitry to retrieve the set of parameter data from the memory based on the initialization state (paragraph 0025, 0026). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 18, Fai and Hoel teach the limitations of the parent claim. Fai teaches: processing circuitry configured to begin executing boot code after the providing of the set of parameters to the set of system elements (paragraph 0020). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 19, Fai teaches: A method comprising: copying a set of parameters associated with a set of computing system elements from a memory to a set of registers (figure 4, element 410; paragraph 0036, 0037); providing the set of parameters from the set of registers to the set of computing system elements (figure 4, element 410; paragraph 0036, 0037); and thereafter, beginning execution of a set of boot code (paragraph 0020). Fai does not explicitly teach: using a DMA block transfer.
Hoel teaches: using a DMA block transfer (paragraph 0025, 0032). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 20, Fai and Hoel teach the limitations of the parent claim. Fai teaches: the set of computing system elements is a first set of computing system elements (figure 1B, element 180a). Fai does not explicitly teach: control circuitry is configured to: detect an initialization state of a second set of system elements; and perform the causing of the DMA circuitry to retrieve the set of parameter data from the memory based on the initialization state.
Hoel teaches: determining an initialization state of a second set of computing system elements (paragraph 0025, 0026); and the copying of the set of parameters from the memory to the set of registers is based on the initialization state (paragraph 0025, 0026). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Allowable Subject Matter
Claims 5 – 8, 10, and 15 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pinilla Pico; et al. US 20200050581 A1
KLINGSTROM; US 20150221635 A1
Cadloni; Gerald L. et al. US 20200082887 A1
Kumar; et al. US 11514990 B1
Roohparvar; US 6260104 B1
cause the DMA circuitry to: retrieve a set of parameter data from a memory; and
store the set of parameter data in the set of registers; and
provide the set of parameter data from the set of registers to a set of system elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111