DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6, 9, 10, 12-18, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US PGPub 2025/0078765) in view of Kim (US PGPub 2023/0317701).
Regarding claim 1, Huang discloses a pixel circuit (fig. 7) comprising:
a light emitting element (fig. 7, organic light-emitting diode O1);
a first switching element (fig. 7, driving transistor DTFT) including a control electrode (gate electrode of DTFT) connected to a first node (fig. 7, node N1), a first electrode connected to a second node (node between T3 and DTFT) and a second electrode connected to a third node (node between DTFT and T4) (fig. 7, collector and emitter electrodes of DTFT), wherein the first switching element (DTFT) applies a driving current to the light emitting element (fig. 7, this is the function of a driving transistor, in this case DTFT);
a first capacitor (fig. 7, first capacitor C1) including a first electrode connected to a fourth node (fig. 7, node N2) and a second electrode connected to the first node (fig. 7, node N1);
a second switching element (fig. 7, first transistor T1) which applies a data voltage to the fourth node (N2) in response to a data writing gate signal ([0093], “A gate electrode of the first transistor T1 is electrically coupled to the first scanning end G1, a source electrode of the first transistor T1 is electrically coupled to the data line DT, and a drain electrode of the first transistor T1 is electrically coupled to the second node N2”);
a third switching element (fig. 7, second transistor T2) which connects the first node (node N1) and the third node (node between DTFT and T4) to each other in response to a path activation gate signal ([0093], “A gate electrode of the second transistor T2 is electrically coupled to the second scanning end G2, a source electrode of the second transistor T2 is electrically coupled to the first node N1, and a drain electrode of the second transistor T2 is electrically coupled to the drain electrode of the driving transistor DTFT”);
a fourth switching element (fig. 7, seventh transistor T7) which applies a reference voltage (VR1) to the fourth node (N2) in response to the path activation gate signal ([0093], “A gate electrode of the seventh transistor T7 is electrically coupled to the second scanning end G2, a source electrode of the seventh transistor T7 is electrically coupled to the first reference voltage end VR1, and a drain electrode of the seventh transistor T7 is electrically coupled to the second node N2”);
a fifth switching element (fig. 7, third transistor T3) which applies a first power voltage to the second node in response to a first emission signal ([0093], “A gate electrode of the third transistor T3 is electrically coupled to the first light-emission control end EM1, a source electrode of the third transistor T3 is electrically coupled to the power source voltage end VDD, and a drain electrode of the third transistor T3 is electrically coupled to the source electrode of the driving transistor DTFT”); and
a sixth switching element (fig. 7, fourth transistor T4) which connects the third node and an anode electrode of the light emitting element to each other in response to a second emission signal ([0093], “A gate electrode of the fourth transistor T4 is electrically coupled to the second light-emission control end EM2, a source electrode of the fourth transistor T4 is electrically coupled to the drain electrode of the driving transistor DTFT, and a drain electrode of the fourth transistor T4 is electrically coupled to an anode of the organic light-emitting diode O1”);
a seventh switching element (fig. 7, sixth transistor T6) which applies an initialization voltage to the anode electrode of the light emitting element in response to ([0093], “A gate electrode of the sixth transistor T6 is electrically coupled to the second resetting control end R2, a source electrode of the sixth transistor T6 is electrically coupled to the second initial voltage end I2, and a drain electrode of the sixth transistor T6 is electrically coupled to the anode of the organic light-emitting diode O1”)
While Huang teaches the fifth and seventh transistors connected to separate gate signal lines, it has been known to connect the fifth and seventh transistors to the same gate signal line. In a similar field of endeavor of pixel circuits, Kim discloses a fifth switching element which applies a first power voltage to the second node in response to a first emission signal ([0071] and fig. 4, “A gate electrode of the fifth transistor T5 may be connected to the light emission control line GL4, a first electrode of the fifth transistor T5 may be connected to the driving voltage line VL1, and a second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1”); and
a seventh switching element which applies an initialization voltage to the anode electrode of the light emitting element in response to the first emission signal (fig. 4 and [0077], “A first gate electrode of seventh transistor T7 may be connected to the light emission control line GL4, a first electrode of seventh transistor T7 may be connected to the first electrode of a first light emitting diode LEDa, and a second electrode of seventh transistor T7 may be connected to the second initialization voltage line VL4”),
wherein the same first emission signal is applied to control the fifth switching element and the seventh switching element such that when the fifth switching element is turned on the seventh switching element is turned off, and when the fifth switching element is turned off the seventh switching element is turned on (fig. 4, light emission control signal EM is connected to transistors T5 and T7 where when T5 is turned on then T7 is turned off and when T5 is turned off then T7 is turned on; also see [0077], “When the gate-on voltage (high voltage) of the light emission control signal EM is applied to the first gate electrode and the seventh transistor T7 is turned on” where T7 is an nmos transistor and T5 is a pmos).
In view of the teachings of Huang and Kim, it would have been obvious to one of ordinary skill in the art to include the fifth and seventh transistors and connections of Kim within the pixel circuitry of Huang, for the purpose of including an emission control transistor and an initialization transistor while minimizing space due to the number of signal lines.
Regarding claim 2, the combination of Huang and Kim further discloses wherein the first switching element is a P-type transistor (Huang: [0111], DTFT is a p-type transistor),
wherein the second switching element is an N-type transistor (Huang: [0116], “The pixel circuit in FIG. 11 differs from that in FIG. 9 in that T1 is an n-type oxide transistor”),
wherein the third switching element is an N-type transistor (Huang: [0111], “The pixel circuit in FIG. 9 differs from that in FIG. 7 in that T2 and T7 are n-type transistors”), and
wherein the fourth switching element is an N-type transistor (Huang: [0111], “The pixel circuit in FIG. 9 differs from that in FIG. 7 in that T2 and T7 are n-type transistors”).
Regarding claim 5, the combination of Huang and Kim further discloses wherein the fifth switching element is a P-type transistor (Kim: [0071], “The fifth transistor T5 may be a P-type transistor”), and
wherein the seventh switching element is an N-type transistor (Kim: [0077], “The seventh transistor T7 that initializes the first electrode of the second light emitting diode LEDb may be an N-type transistor”).
Regarding claim 6, the combination of Huang and Kim further disclose wherein the sixth switching element is a P-type transistor (Huang: [0111], transistor T4 is a p-type).
Regarding claim 9, the combination of Huang and Kim further discloses further comprising:
an eighth switching element (Huang: fig. 7, eight transistor T8) which applies a bias voltage to the second node in response to a bias gate signal (Huang: [0093], “A gate electrode of the eighth transistor T8 is electrically coupled to the second resetting control end R2, a source electrode of the eighth transistor T8 is electrically coupled to the second reference voltage end VR2, and a drain electrode of the eighth transistor T8 is electrically coupled to the source electrode of the driving transistor DTFT”).
Regarding claim 10, the combination of Huang and Kim further discloses further comprising:
a second capacitor (Huang: fig. 7, second capacitor C2) including a first electrode which receives the first power voltage (Huang: fig. 7, VDD) and a second electrode connected to the fourth node (Huang: fig. 7, node N2).
Regarding claim 12, the combination of Huang and Kim further discloses wherein the second switching element includes a control electrode which receives the data writing gate signal, a first electrode which receives the data voltage and a second electrode connected to the fourth node (Huang: [0093], “A gate electrode of the first transistor T1 is electrically coupled to the first scanning end G1, a source electrode of the first transistor T1 is electrically coupled to the data line DT, and a drain electrode of the first transistor T1 is electrically coupled to the second node N2”),
wherein the third switching element includes a control electrode which receives the path activation gate signal, a first electrode connected to the first node and a second electrode connected to the third node (Huang: [0093], “A gate electrode of the second transistor T2 is electrically coupled to the second scanning end G2, a source electrode of the second transistor T2 is electrically coupled to the first node N1, and a drain electrode of the second transistor T2 is electrically coupled to the drain electrode of the driving transistor DTFT”), and
wherein the fourth switching element includes a control electrode which receives the path activation gate signal, a first electrode connected to the fourth node and a second electrode which receives a reference voltage (Huang: [0093], “A gate electrode of the seventh transistor T7 is electrically coupled to the second scanning end G2, a source electrode of the seventh transistor T7 is electrically coupled to the first reference voltage end VR1, and a drain electrode of the seventh transistor T7 is electrically coupled to the second node N2”).
Regarding claim 13, the combination of Huang and Kim further discloses wherein the fifth switching element (Huang: fig. 7, third transistor T3) includes a control electrode which receives the first emission signal, a first electrode which receives the first power voltage and a second electrode connected to the second node (Huang: [0093], “A gate electrode of the third transistor T3 is electrically coupled to the first light-emission control end EM1, a source electrode of the third transistor T3 is electrically coupled to the power source voltage end VDD, and a drain electrode of the third transistor T3 is electrically coupled to the source electrode of the driving transistor DTFT”),
wherein the sixth switching element (Huang: fig. 7, fourth transistor T4) includes a control electrode which receives the second emission signal, a first electrode connected to the third node and a second electrode connected to the anode electrode of the light emitting element (Huang: [0093], “A gate electrode of the fourth transistor T4 is electrically coupled to the second light-emission control end EM2, a source electrode of the fourth transistor T4 is electrically coupled to the drain electrode of the driving transistor DTFT, and a drain electrode of the fourth transistor T4 is electrically coupled to an anode of the organic light-emitting diode O1”),
wherein the seventh switching element (Huang: fig. 7, sixth transistor T6 and Kim: fig. 4, seventh transistor T7) including a control electrode which receives the first emission signal, a first electrode which receives the initialization voltage and a second electrode connected to the anode electrode of the light emitting element (Kim: [0077], “A first gate electrode of seventh transistor T7 may be connected to the light emission control line GL4, a first electrode of seventh transistor T7 may be connected to the first electrode of a first light emitting diode LEDa, and a second electrode of seventh transistor T7 may be connected to the second initialization voltage line VL4”),
further comprising:
an eighth switching element (Huang: fig. 7, eighth transistor T8) including a control electrode which receives a bias gate signal, a first electrode which receives a bias voltage and a second electrode connected to the second node (Huang: [0093], “A gate electrode of the eighth transistor T8 is electrically coupled to the second resetting control end R2, a source electrode of the eighth transistor T8 is electrically coupled to the second reference voltage end VR2, and a drain electrode of the eighth transistor T8 is electrically coupled to the source electrode of the driving transistor DTFT”); and
a second capacitor (Huang: fig. 7, second capacitor C2) including a first electrode which receives the first power voltage and a second electrode connected to the fourth node (Huang: [0093], “A first end of the second capacitor C2 is electrically coupled to the second node N2, and a second end of the second capacitor C2 is electrically coupled to the power source voltage end VDD”).
Regarding claim 14, the combination of Huang and Kim further discloses wherein in an initialization period, the first emission signal has an inactive level, the second emission signal has an active level, the path activation gate signal has an active level, the data writing gate signal has an inactive level and the bias gate signal has an inactive level (Huang: fig. 8A, time period just before S1).
Regarding claim 15, the combination of Huang and Kim further discloses wherein in a compensation period, the first emission signal has an active level, the second emission signal has an inactive level, the path activation gate signal has an active level, the data writing gate signal has an inactive level and the bias gate signal has an inactive level (Huang: fig. 8A, time period of compensation phase S2).
Regarding claim 16, the combination of Huang and Kim further discloses wherein in a data writing period, the first emission signal has an inactive level, the second emission signal has an inactive level, the path activation gate signal has an inactive level, the data writing gate signal has an active level and the bias gate signal has an inactive level (Huang: fig. 8A, time period S3 and S4).
Regarding claim 17, the combination of Huang and Kim further discloses wherein in a bias period, the first emission signal has an inactive level, the second emission signal has an inactive level, the path activation gate signal has an inactive level, the data writing gate signal has an inactive level and the bias gate signal has an active level (Huang: fig. 8A, time period after S4).
Regarding claim 18, the combination of Huang and Kim further discloses wherein the path activation gate signal maintains an active level in an initialization period and a compensation period and in a period between the initialization period and the compensation period (Huang: fig. 8A, G2 is low during entire time of t2).
Regarding claim 20, the combination of Huang and Kim further discloses wherein the first emission signal and the second emission signal are generated from a same signal generator (Huang: [0059], “The first light-emission control circuitry 21 is electrically coupled to a first light-emission control end EM1, the power source voltage end VDD and the first end of the driving circuitry 10, and configured to control the power source voltage end VDD to be electrically coupled to the first end of the driving circuitry 10 under the control of a first light-emission control signal from the first light-emission control end EM1. The second light-emission control circuitry 22 is electrically coupled to a second light-emission control end EM2, the second end of the driving circuitry 10 and the first electrode of the light-emitting element E1, and configured to control the second end of the driving circuitry 10 to be electrically coupled to the first electrode of the light-emitting element E1 under the control of a second light-emission control signal from the second light-emission control end EM2”).
Regarding claim 21, the combination of Huang and Kim further discloses
wherein in an initialization period, the first emission signal has an inactive level, the second emission signal has an active level and the path activation gate signal has an active level (Huang: fig. 8A, time period S1), and
wherein in a compensation period subsequent to the initialization period, the first emission signal has an active level, the second emission signal has an inactive level and the path activation gate signal has the active level (Huang: fig. 8A, time period S2).
Claims 11, 19 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Huang and Kim in view of Noh et al. (US PGPub 2024/0194139)
Regarding claim 11, while the combination of Huang and Kim discloses a first and second capacitor, different specific structures and locations of capacitors within a pixel circuitry have been know. In a similar field of endeavor of display devices, Noh discloses wherein the first capacitor is formed between a first metal layer and a second metal layer disposed on the first metal layer ([0142], “In the exemplary embodiment, the first capacitor C1 may include a storage capacitor. The storage capacitor may be a component which charges an electric energy (for example, charges or a data voltage) to maintain a constant voltage for one frame. For example, when the input of the voltage stops during the process of driving a pixel circuit, the first capacitor C1 supplies a stored electric energy to the driving transistor DT to maintain the driving of the driving transistor DT during one frame. The first capacitor C1 may be configured by a parasitic capacitor which is an internal capacitor. However, it is not limited thereto and the first capacitor may be an external capacitor disposed at the outside of the driving transistor DT.”),
wherein the second capacitor is formed between the second metal layer and a third metal layer disposed on the second metal layer ([0143], “In the exemplary embodiment, the second capacitor C2 may be connected to the high potential power line and the second transistor T2. For example, the second capacitor C2 may be connected between the high potential power line and the second transistor T2. A capacity of the second capacitor C2 may be equal to or larger than a capacity of the first capacitor C1” and [0084], “In this case, the first light shielding layer 208 of the driving transistor 260 is configured by a metal layer, such as titanium having an ability to collect hydrogen particles. Further, the first light shielding layer 208 is enclosed by a silicon nitride SiNx layer having an ability to collect hydrogen particles so that the reliability of the oxide semiconductor pattern by suppressing the hydrogen particles from reaching the first oxide semiconductor pattern 211 may be ensured”), and
wherein the first capacitor and the second capacitor overlap each other (fig. 2).
In view of the teachings of Huang, Kim and Noh, it would have been obvious to one of ordinary skill in the art to arrange the capacitor configuration of Noh, within the system of Huang and Kim, for the purpose of rearranging a known configuration to improve a user’s experience such as by reducing a flicker phenomenon (Noh: [0144]).
Regarding claim 19, the combination of Huang and Kim further discloses wherein the path activation gate signal has an active level in an initialization period and a compensation period (Huang: fig. 8A, G2 is low during entire time of t2). While Huang and Kim discloses a constant voltage for a gate signal, it has been known to provide a series of pulses instead of a constant voltage. In a similar field of endeavor of display devices, Noh discloses wherein the path activation gate signal has an inactive level in a period between the initialization period and the compensation period (fig. 8, SC1 shown as a series of pulses).
In view of the teachings of Huang, Kim and Noh, it would have been obvious to one of ordinary skill in the art to use the pulse signals of Noh within the system of Huang and Kim, where using pulses instead of a constant voltage has been known to provide better stability.
Regarding claim 27, the combination of Huang and Kim discloses a display apparatus comprising:
a display panel (Huang: [0161], display device) including a pixel circuit (Huang: [0161], pixel circuit);
wherein the pixel circuit comprises the circuitry of claim 1 and is therefore interpreted and rejected based on similar reasoning.
While Huang and Kim discloses a display device in general and discloses gate signals and a data signal it has been known to use drivers within a display device to drive pixel circuitry. In a similar field of endeavor of display devices, Noh discloses a gate driver (fig. 1, gate driver 13) which applies a gate signal to the pixel circuit ([0038], “a gate driver (gate driving circuit) 13 which drives gate lines 15”); and
a data driver (fig. 1, data driver 12) which applies a data voltage to the pixel circuit ([0038], “a data driver (data driving circuit) 12 which drives data lines 14”).
In view of the teachings of Huang, Kim and Noh, it would have been obvious to one of ordinary skill in the art to use the drivers of Noh within the display apparatus of Huang and Kim, for the purpose of providing known circuitry to perform the pixel driving functions.
Claims 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Seo et al. (US PGPub 2023/0290313).
Regarding claim 22, Huang discloses a display panel ([0161], display device) comprising:
wherein at least one
a light emitting element (fig. 7, organic light-emitting diode O1);
a first switching element (fig. 7, driving transistor DTFT) including a control electrode connected to a first node (fig. 7, node N1), a first electrode connected to a second node and a second electrode connected to a third node (fig. 7), wherein the first switching element applies a driving current to the light emitting element (fig. 7, this is the function of a driving transistor);
a first capacitor (fig. 7, first capacitor C1) including a first electrode connected to a fourth node (fig. 7, node N2) and a second electrode connected to the first node (fig. 7, node N1);
a second switching element (fig. 7, first transistor T1) which applies a data voltage to the fourth node in response to a data writing gate signal ([0093], “A gate electrode of the first transistor T1 is electrically coupled to the first scanning end G1, a source electrode of the first transistor T1 is electrically coupled to the data line DT, and a drain electrode of the first transistor T1 is electrically coupled to the second node N2”);
a third switching element (fig. 7, second transistor T2) which connects the first node and the third node to each other in response to a path activation gate signal ([0093], “A gate electrode of the second transistor T2 is electrically coupled to the second scanning end G2, a source electrode of the second transistor T2 is electrically coupled to the first node N1, and a drain electrode of the second transistor T2 is electrically coupled to the drain electrode of the driving transistor DTFT”); and
a fourth switching element (fig. 7, seventh transistor T7) which applies a reference voltage to the fourth node in response to the path activation gate signal ([0093], “A gate electrode of the seventh transistor T7 is electrically coupled to the second scanning end G2, a source electrode of the seventh transistor T7 is electrically coupled to the first reference voltage end VR1, and a drain electrode of the seventh transistor T7 is electrically coupled to the second node N2”).
While Huang discloses a display device in general including at least one pixel with specific circuitry, it has been known that display devices include display panels with a plurality of pixels. In a similar field of endeavor of display devices Seo discloses, a first pixel, a second pixel, a third pixel and a fourth pixel, which are sequentially disposed in a first pixel row (fig. 7); and
a fifth pixel, a sixth pixel, a seventh pixel and an eighth pixel, which are sequentially disposed in a second pixel row (fig. 7);
wherein the display panel further comprises a first data writing gate line connected to the first pixel, the second pixel, the third pixel and the fourth pixel, a second data writing gate line connected to the fifth pixel, the sixth pixel, the seventh pixel and the eighth pixel, a first data line connected to the first pixel and the fifth pixel, a second data line connected to the second pixel and the sixth pixel, a third data line connected to the third pixel and the seventh pixel, and a fourth data line connected to the fourth pixel and the eighth pixel (fig. 7, scan lines SL1 and SL2 and data lines DA1, DB1, DA2 and DB2).
In view of the teachings of Huang and Seo, it would have been obvious to one of ordinary skill in the art to include the plurality of pixels of Seo within the display device of Huang, as it is known that display devices contain a plurality of pixels circuits in an array in order to improve a user’s experience.
Regarding claim 23, the combination of Huang and Seo further discloses further comprising:
a first switch which activates the first data line in response to a first selection signal (Seo: fig. 7, switch MA1);
a second switch which activates the second data line in response to the first selection signal (Seo: fig. 7, switch MA2);
a third switch which activates the third data line in response to a second selection signal (Seo: fig. 7, switch MB1); and
a fourth switch which activates the fourth data line in response to the second selection signal (Seo: fig. 7, switch MB2).
Regarding claim 24, the combination of Huang and Seo further discloses wherein the first data line and the third data line are connected to each other (Seo: fig. 7, where DA1 is the first data line and DB1 is the third data line), and
wherein the second data line and the fourth data line are connected to each other (Seo: fig. 7, where DA2 is the second data line and DB2 is the fourth data line).
Regarding claim 25, the combination of Huang and Seo further discloses wherein in a first timing, a first data writing gate signal applied to the first data writing gate line has an active level and the first selection signal has an active level, wherein in a second timing, the first data writing gate signal has the active level and the second selection signal has an active level, wherein in a third timing, a second data writing gate signal applied to the second data writing gate line has an active level and the first selection signal has the active level, and wherein in a fourth timing, the second data writing gate signal has the active level and the second selection signal has the active level (Seo: fig. 8 and [0129], “FIG. 8 illustrates section Si in which a data signal corresponding to an i-th scan line SLi is applied, and section Si+1 in which a data signal corresponding to an i+1-th scan line SLi+1 is applied (where i is a natural number). Furthermore, FIG. 8 illustrates a data signal DATA [j] to be applied to a j-th data line DLj (where j is a natural number)”).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Seo further in view of Lee et al. (US PGPub 2024/0071307).
Regarding claim 26, while the combination of Huang and Seo teaches a first-fourth data line, it has been known to place multiple data lines between pixels. In a similar field of endeavor of display devices, Lee discloses wherein the first data line and the second data line are disposed between the first pixel and the second pixel, and wherein the third data line and the fourth data line are disposed between the third pixel and the fourth pixel (fig. 2, DL1E and DL20 are between pixels and the array would be repeated).
In view of the teachings of Huang, Seo, and Lee, it would have been obvious to one of ordinary skill in the art to place a plurality of data lines between pixels, as taught by Lee, within the system of Huang and Seo for the purpose of rearranging part based on availability of space.
Response to Arguments
Applicant’s arguments, see pages 13-16, filed 02/02/2026, with respect to the rejection(s) of claim(s) 1 and 22 under 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim and Seo.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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