Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/27/2025 has been considered by the examiner.
Oath/Declaration
Oath/Declaration as file 12/02/2024 is noted by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 21-33 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, (1+2) and 3-13 of U.S. Patent No. 12,158,508 (Application No. 18/148506) respectively. Although the conflicting claims are not identical, they are not patentably distinct from each other because both sets of claims cover the same subject matter.
Both independent claims’ features of the instant application and the co-pending application can be compared as:
Instant Application: Claim 21
US Patent 12,158,508: Claim 1
An apparatus for ground fault monitoring comprising:
An apparatus for ground fault monitoring comprising:
a first midpoint grounding resistor coupled with a first voltage bus line, the first midpoint grounding resistor creating a first current flow path between the first voltage bus line and a common ground node;
a high resistance midpoint grounding (HRMG) current limiting circuit comprising: a first HRMG resistor coupled with the first voltage bus line, wherein a first current flowing through the first HRMG resistor from the first voltage bus line flows toward a common ground node;
a second midpoint grounding resistor coupled with a second voltage bus line, the second midpoint grounding resistor creating a first current flow path between the second voltage bus line and the common ground node;
a second HRMG resistor coupled with the second voltage bus line, wherein a second current flowing through the second HRMG resistor from the common ground node flows toward the second voltage bus line;
a first transistor having a base terminal and an emitter terminal;
a first transistor having a base terminal and an emitter terminal
a second transistor having a base terminal and an emitter terminal;
a second transistor having a base terminal and an emitter terminal
a positive sense resistor coupled across the base and emitter terminals of the first transistor;
a positive sense resistor; wherein the positive sense resistor is coupled across the base and emitter terminals of the first transistor;
a negative sense resistor coupled across the base and emitter terminals of the second transistor; and
a negative sense resistor; wherein the negative sense resistor is coupled across the base and emitter terminals of the second transistor;
a ground fault signal line configured to transmit a ground fault signal indicative of one of a ground fault condition existing between the first voltage bus line and the common ground node and a ground fault condition existing between the second voltage bus line and the common ground node.
wherein the ground fault sense circuit is configured to generate a ground fault signal indicative of a ground fault condition existing between the first voltage bus line and the common ground node and between the second voltage bus line and the common ground node.
Both sets of claims’ features of the instant application (claim 22-33) and the US Patent (claims (1+2) and 3-13) can be compared by using the table shown above.
This is a double patenting rejection since the conflicting claims have been patented.
Allowable Subject Matter
The following is an examiner’s statement of reasons for allowance (Should the Double Patenting Rejection be overcome):
Regarding claim 21, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 21,
“…a second midpoint grounding resistor coupled with a second voltage bus line, the second midpoint grounding resistor creating a first current flow path between the second voltage bus line and the common ground node; a first transistor having a base terminal and an emitter terminal; a second transistor having a base terminal and an emitter terminal; a positive sense resistor coupled across the base and emitter terminals of the first transistor; a negative sense resistor coupled across the base and emitter terminals of the second transistor; and a ground fault signal line configured to transmit a ground fault signal indicative of one of a ground fault condition existing between the first voltage bus line and the common ground node and a ground fault condition existing between the second voltage bus line and the common ground node.”
Claims 22-33 are also allowed as they further limit allowed claim 21.
Regarding claim 34, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 34,
“…a positive sense resistor coupled between the first midpoint grounding resistor and a first voltage bus line; a negative sense resistor coupled between the second midpoint grounding resistor and the first voltage bus line; and a first transistor comprising: a base terminal coupled to a common node between the first midpoint grounding resistor and a first terminal of the positive sense resistor; an emitter terminal coupled to a second terminal of the positive sense resistor; and a collector terminal; a second transistor comprising: a base terminal coupled to a common node between the second midpoint grounding resistor and a first terminal of the negative sense resistor; an emitter terminal coupled to a second terminal of the negative sense resistor; and a collector terminal; and a ground fault signal line coupled to the collector terminal of the first transistor and to the collector terminal of the second transistor; wherein the ground fault signal line is configured to transmit a ground fault signal indicative of one of a ground fault condition existing between the first voltage bus line and the common ground.”
Claims 35-40 are also allowed as they further limit allowed claim 34.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shaak et al. US 2008/0278871 - A circuit breaker includes for each neutral and phase power conductor, a current sensor sensing an alternating current flowing in a corresponding power conductor, a comparator determining whether the sensed alternating current is positive or negative, a rectifier rectifying the sensed alternating current to provide a rectified current value, and an analog-to-digital converter converting the rectified current value to a signed digital value having a positive sign. A processor cooperates with the comparators and the analog-to-digital converters and includes a routine that changes the positive sign of the signed digital value to a negative sign if the sensed alternating current is negative, adds the signed digital value for each power conductor to provide a sum, and employs the sum to determine whether to output a ground fault signal.
Telefus et al. US 2024/0178653 - A device comprises current sense circuitry, analog-to-digital converter circuitry, and digital signal processing circuitry. The current sense circuitry is configured to sense a first current flowing in a first wire and a second current flowing in a second wire, the first and second wires being configured to supply AC power to a load coupled to the device. The analog-to-digital converter circuitry is configured to generate first digital data corresponding to the first current, and second digital data corresponding to the second current.
Kaufman US 2018/0294712 - A power conversion topology and control method intended for use with a DC bus is disclosed, providing a means to prevent the flow of ground fault current while detecting a fault condition and optionally continuing to operate the DC bus. In one control configuration, a DC-DC power stage with an active current control loop drives differential current to zero, and a separate voltage control loop maintains the desired differential bus voltage. Absolute bus voltage with respect to ground is monitored in order to detect fault conditions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAUL J RIOS RUSSO whose telephone number is (571)270-3459. The examiner can normally be reached Monday-Friday: 10am-6pm, EST.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858
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