DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-8,10-14,18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2, recites the limitation "a second transistor connected between the data line and the first node, wherein the second transistor is turned on in response to the second scan signal". The specification as filed does not describe where the second transistor is turned on in response to the second scan signal as claimed.
Claim 4, recites the limitation "an eighth transistor connected between the third node and a third power line that provides a voltage of a second power source, wherein the eighth transistor is turned on in response to the fifth scan signal."
However, the specification as filed does not describe an eight transistor connected between the third node and a third power line transistor that is turned on in response to the fifth scan signal, as claimed.
Claim 10, recites the limitation "a second transistor connected between the data line and the first node, wherein the second transistor is turned on in response to the second scan signal... wherein the fourth transistor is turned on in response to the first scan signal... a seventh transistor connected between the second node and the first electrode of the light emitting element, wherein the seventh transistor includes a gate electrode connected to the first node."
The specification as filed does not describe a pixel configuration where the second transistor is turned on in response to the second scan signal. Similarly, the specification as filed does not describe the fourth transistor is turned in response to the first scan signal as claimed, and does not describe a transistor connected between the second node and the light emitting element, wherein it includes a gate electrode connected to the first node, as claimed.
Claim 11, recites "an eighth transistor connected between the first electrode of the light emitting element and a third power line that provides a voltage of a second power source, wherein the eighth transistor is turned on in response to the first scan signal" However, the specification as filed does not describe eight transistor is turned in response to the first scan signal as claimed.
Claim 15, recites "a seventh transistor connected between the first electrode of the light emitting element and a third power line that provides a voltage of a second power source, wherein the seventh transistor is turned on in response to the first scan signal" However, the specification does not describe such pixel configuration, in which a transistor connected between the first electrode of the light emitting element and a third power line that provides a voltage of a second power source is turned in response to the first scan signal as claimed.
Claim 15, further recites "an eighth transistor connected between the second node and the first electrode of the light emitting element, wherein the eighth transistor includes a gate electrode connected to a gate electrode of the seventh transistor" The specification not describe where the eight transistor includes a gate electrode connected to the gate of the seventh transistor, as claimed.
Claim 18, recites "a fourth transistor connected between the first node and a first power line that provides a voltage of a first power source wherein the fourth transistor is turned on in response to the third scan signal....a seventh transistor connected between the first electrode of the light emitting element and a third power line that provides a voltage of a second power source, wherein the seventh transistor is turned on in response to the third scan signal" The specification as filed does not describe a fourth transistor connected between the first node and first power that is turned on in response to the third scan signal as claimed. Similarly, the specification does not describe where a seventh transistor connected between the first electrode of the light emitting element and a third power line, and is turned on in response to the third scan signal, as claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7,9,15-16,21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (US 2024/0257739) in view of Park et al. (US 2018/0226029).
As to Claim 1, Noh et al. discloses As to Claim 1, Noh et al. disclose A display device, comprising: a pixel including a light emitting element (fig.3, light emitting diode LD; para.0077) and a first transistor (fig.3, transistor T1) connected between a first node (fig.3, node N1) and a second node (fig.3, node N3), wherein the first transistor is configured to generate a driving current (fig.3, para.0081- transistor T1 may control a driving current),
wherein the pixel is connected to a first scan line (fig.3, scan line S1i), a second scan line (fig.3,
scan line S2i), a third scan line (fig.3, scan line S3i), a fourth scan line (fig.3, scan line S4i), a fifth scan line, an emission control line (fig.3, emission control line Ei), and a data line (fig.3, data line Dj);
an emission driver configured to supply an emission control signal to the emission control line (fig.1, emission driver 300; para.0055);
a scan driver configured to supply first to fifth scan signals respectively to the first to fifth [fourth] scan lines (fig.1, scan driver 200; para. 0053) in a period in which the emission control signal is supplied (fig.4, para.0117-0118; scan signals SC1i, SC2i, SC3i, SC4i are supplied to the first to third scan lines S1i, S2i, S3i, S4i, respectively during the non-emission period NEP1 in which the emission control signal Emi is supplied); and
a data driver configured to supply a data signal to the data line (fig.1, data driver 400; para.0058),
wherein the first scan signal controls a timing at which the second node and a first electrode of the light emitting element are connected to each other,
Noh et al. does not expressly disclose a fifth scan signal, and wherein the first scan signal controls a timing at which the second node and a first electrode of the light emitting element are connected to each other.
Park et al. discloses driving transistor TD connected between a first node N1 and second node N2, where the second node is connected to the light emitting element OLED, and a transistor connected between the first and second node, where the transistor may be turned in response to a scan signal Scan(k+1), so that the initialization time may be reduced (para.0068, 0073, 0085-0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Noh et al. with the teachings of Park et al., such that a transistor (as disclosed by Park) may be connected between nodes N3 and N4, in parallel with emission control transistor T6 (of Noh). The motivation being to reduce the initialization time of the emission control transistor.
As to Claim 2, Noh et al. in view of Park et al, disclose wherein the pixel further includes: a second transistor connected between the data line and the first node, wherein the second transistor is turned on in response to the second scan signal (Noh-fig.3, transistor T3, connected between data line Dj and first node N1, gate connected to scan line S2i); a third transistor connected between the second node and a third node to which a gate electrode of the first transistor is connected, wherein the third transistor is turned on in response to the third scan signal (Noh-fig.3, transistor T2, connected between second node N3 and third node N2 which connected to gate of transistor T1, and gate connected to scan line S1i); a fourth transistor connected between the first node and a first power line that provides a voltage of a first power source, wherein the fourth transistor is turned on in response to the fourth scan signal (Noh-fig.3, transistor T8, connected between first node N1 and power line PL5, gate connected to scan line S4i); a fifth transistor connected between a second power line that provides a driving power source and the first node, wherein the fifth transistor is turned off in response to the emission control signal (Noh-fig.3, transistor T5, connected between power line PL1(Vdd) and first node N1, and gate to emission control line Ei); a sixth transistor connected between the second node and the first electrode of the light emitting element, wherein the sixth transistor is turned off in response to the emission control signal supplied to the emission control line (Noh-fig.3, transistor T6, connected between second node N3 and the anode of light emitting LD, gate connected to emission control line Ei); and a seventh transistor connected between the second node and the first electrode of the light emitting element, wherein the seventh transistor is turned on in response to the first scan signal (Park-fig.7, transistor T4, connected between second node N3 and node N4 (corresponding to first electrode of LD), and scan signal Scank+1).
As to Claim 3, Noh et al. in view of Park et al., disclose wherein, after the scan driver supplies the fourth scan signal to the fourth scan line (Noh- fig.4, para.0119; period S2, scan signal SC4i supplied to fourth scan line S4i), the scan driver supplies the first scan signal to the first scan line (Noh-fig.4,period S3-S4, scan signal SC3i is supplied to scan line S3i).
As to Claim 4, Noh et al. in view of Park et al. disclose, wherein the pixel further includes: an eighth transistor connected between the third node and a third power line that provides a voltage of a second power source, wherein the eighth transistor is turned on in response to the fifth scan signal (Noh-fig.3, transistor T4, connected between third node N2 and power line PL3, gate connected to scan line S3i).
As to Claim 5, Noh et al. in view of Park et al. disclose wherein the pixel further includes: a ninth transistor connected between the first electrode of the light emitting element and a fourth power line that provides a voltage of a third power source, wherein the ninth transistor is turned on in response to the fourth scan signal (Noh-fig.3, transistor T7, connected between anode of LD and power line PL4, gate connected to scan signal S4i).
As to Claim 6, Noh et al. in view of Park et al., disclose wherein one frame period includes a plurality of non-emission periods divided by the emission control signal (Noh-fig.4-5, non-emission period NEP1 includes first to sixth periods S1-S6 and second non emission period NEP2 include period S7; para.0116), wherein the scan driver supplies the fourth scan signal in the non-emission periods (Noh-fig.4, scan signal SC4i {read as fourth scan signal} is supplied in both non emission periods NEP1 and NEP2), and wherein the scan driver supplies the first scan signal (Noh-fig.4; Park-scan signal of transistor T4), the second scan signal (Noh-fig.4-SC2i), the third scan signal (Noh-fig.4-SC1i), and the fifth scan signal (Noh-fig.4, SC3i) in only a first non-emission period among the non-emission periods (Noh-fig.4,
are supplied in only in NEP1),
As to Claim 7, Noh et al.in view of Park et al. disclose wherein the first non-emission period includes a first period and a second period subsequent to the first period (Noh-fig.4-5, non-emission period NEP1 includes first to sixth periods S1-S6 (periods S2 and S3 {read as first and second periods respectively}); para.0116), and wherein the scan driver is further configured to: supply the fourth scan signal to the fourth scan line in the first period (fig.4, SC4i in period S2); and supply the first scan signal to the first scan line in the second period (Noh-fig.4; Park-fig.7, scan signal Scan(k+1) of T4).
As to Claim 9, Noh et al. discloses A display device, comprising: a pixel including a light emitting element (fig.3, light emitting diode LD; para.0077) and a first transistor (fig.3, transistor T1) connected between a first node (fig.3, node N1) and a second node (fig.3, node N3 {read as second node}), wherein the first transistor is configured to generate a driving current (fig.3, para.0081- transistor T1 may control a driving current),
wherein the pixel is connected to a first scan line (fig.3, scan line S1i), a second scan line (fig.3, scan line S2i), a third scan line (fig.3, scan line S3i), a fourth scan line (fig.3, scan line S4i), an emission control line (fig.3, emission control line Ei), and a data line (fig.3, data line Dj);
an emission driver configured to supply an emission control signal to the emission control line (fig.1, emission driver 300; para.0055); a scan driver configured to supply first to fourth scan signals respectively to the first to fourth scan lines (fig.1, scan driver 200; para. 0053) in a period in which the emission control signal is supplied (fig.4, para.0117-0118; scan signals SC1i, SC2i, SC3i, SC4i are supplied to the first to third scan lines S1i, S2i, S3i, S4i, respectively during the non-emission period NEP1 in which the emission control signal Emi is supplied); and a data driver configured to supply a data signal to the data line (fig.1, data driver 400; para.0058),
wherein the first scan signal controls a timing at which the second node and a first electrode of the light emitting element are connected to each other
Noh et al. does not expressly disclose wherein the first scan signal controls a timing at which the second node and a first electrode of the light emitting element are connected to each other
Park et al. discloses driving transistor TD connected between a first node N1 and second node N2, where the second node is connected to the light emitting element OLED, and a transistor connected between the first and second node, where the transistor may be turned in response to a scan signal Scank+1, so that the initialization time may be reduced (para.0068, 0073, 0085-0087).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Noh et al. with the teachings of Park et al., such that a transistor (as disclosed by Park) may be connected between nodes N3 and N4, in parallel with emission control transistor T6 (of Noh). The motivation being to reduce the initialization time of the emission control transistor.
As to Claim 15, Noh et al. in view of Park et al. disclose wherein the pixel further includes: a second transistor connected between the data line and the first node, wherein the second transistor is turned on in response to the second scan signal (Noh-fig.3, transistor T3, connected between data line Dj and first node N1, gate connected to scan line S2i); a third transistor connected between the second node and a third node connected to the gate electrode of the first transistor, wherein the third transistor is turned on in response to the third scan signal (Noh-fig.3, transistor T2, connected between second node N3 and third node N2 which connected to gate of transistor T1, and gate connected to scan line S1i); a fourth transistor connected between the first node and a first power line that provides a voltage of a first power source, wherein the fourth transistor is turned on in response to the first scan signal (Noh-fig.3, transistor T8, connected between first node N1 and power line PL5, gate connected to scan line S4i); a fifth transistor connected between a second power line that provides a driving power source and the first node, wherein the fifth transistor is turned off in response to the emission control signal(Noh-fig.3, transistor T5, connected between power line PL1(Vdd) and first node N1, and gate to emission control line Ei); a sixth transistor connected between the second node and the first electrode of the light emitting element, wherein the sixth transistor is turned off in response to the emission control signal (Noh-fig.3, transistor T6, connected between second node N3 and the anode of light emitting LD, gate connected to emission control line Ei); a seventh transistor connected between the first electrode of the light emitting element and a third power line that provides a voltage of a second power source, wherein the seventh transistor is turned on in response to the first scan signal (Noh-fig.3, transistor T7 connected between anode of LD and power line PL4, and gate connected to scan signal S4i); and an eighth transistor connected between the second node and the first electrode of the light emitting element, wherein the eighth transistor includes a gate electrode connected to a gate electrode of the seventh transistor (Park-fig.7, transistor T4, connect between node N3 and N4 (of Noh), gate connected to scan signal scank+1).
Noh et al. in view of Park et al. do not expressly disclose where the gate of the eight transistor (T4 of Park) connected to a gate of the seventh transistor (T7 of Noh). However, Noh et al. discloses where the gates of transistors T7 and T4 are connected to each other to a same scan S4i. Park et al. discloses where the gate of eigth transistor (T4) is connected to a scan signal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device as disclosed by Noh et al. in view of Park et al., by connecting the gate of transistor T4 (as disclosed by Park) to a gate of transistor T7 (of Noh), since in doing so would not have modified the operation of the device, yielding predictable results. In particular, the seventh transistor and eight transistor are turned on by a same scan signal.
As to Claim 16, Noh et al. in view of Park et al. disclose wherein the pixel further includes: a ninth transistor connected between the third node and a fourth power line that provides a voltage of a third power source, wherein the ninth transistor is turned on in response to the fourth scan signal (Noh-fig.3, transistor T4, between third node N2 and power line PL3, and gate connected to scan S3i).
As to Claim 21 has limitation similar to those of Claim 1 and are met by the references as set forth above. Claim 21, further recites: a processor to provide input image data (Noh-fig.1, para.0051- timing controller 500 receives DATA1 from a host system, such as an application processor); and a display device to display an image based on the input image data (Noh-fig.1, display panel 100).
Response to Arguments
Applicant's arguments filed 01/29/2026, re the 112(b) have been fully considered but they are not persuasive.
Re 112(b) rejection, applicant points to Figures 3, 6, 7,8 corresponding to different embodiments of the claimed invention, and where claimed elements as recited in the claims are not in correspondence with what is labeled in the drawings 01/29/2026, and where a claimed element corresponds to different labeled element in each of the figures.
According to applicant, for Figure 3, “first scan signal” appears to correspond to the “fifth scan signal”, and for Figure 6-7, appears to correspond to the “fourth scan signal”, and in Figure 8 appears to correspond to the “third scan signal”.
As depicted in Figure 3,6,7 and as described in the specification as filed, the “fist scan signal” is in reference to first scan line S1i “[0084] The seventh transistor M7 may be turned on when the first scan signal is supplied to the first scan line S1i”
In Figure 6, “[0126] The pixel PXij may include a light emitting element LD, first to ninth transistors M1 to M9, a first capacitor C1, and a second capacitor C2. The light emitting element LD, the first to ninth transistors M1 to M9, and the first capacitor C1, which are shown in FIG. 6, are similar to the light emitting element LD, the first to ninth transistors M1 to M9, and the first capacitor C1, which are shown in FIG. 3, and therefore, for convenience of explanation, a further description of these components and related technical aspects will be omitted”
In Figure 7, “[0134] The pixel PXij may include a light emitting element LD, first to ninth transistors M1 to M9, and a first capacitor C1. The light emitting element LD, the first to ninth transistors M1 to M9, and the first capacitor C1, which are shown in FIG. 7, are similar to the light emitting element LD, the first to ninth transistors M1 to M9, and the first capacitor C1, which are shown in FIG. 3, and therefore, for convenience of explanation, a further description of these components and related technical aspects will be omitted.”
Figure 8, “[0141] The light emitting element LD, the first to eighth transistors M1 to M8, and the first capacitor C1, which are shown in FIG. 8, are similar to the light emitting element LD, the first to eighth transistors M1 to M8, and the first capacitor C1, which are shown in FIG. 3, and therefore, for convenience of explanation, a further description of these components and related technical aspects will be omitted”
Re Claim 2, recites the limitation “a second transistor connected between the data line and the first node, wherein the second transistor is turned on in response to the second scan signal”.
Applicant pointed to the embodiment of Figure 3, in which the third scan signal S3i is referred to as the “second scan signal” as claimed in claim 2. However, the examiner disagrees.
Parent Claim 1, recites “the pixel connected to a first scan line, a second scan line, a third scan line, a fourth scan line, and a fifth scan line”. As described in the specification as filed, “[0076] The second transistor M2 may be connected between the jth data line Dj (hereinafter, referred to as a data line) and the first node N1. A gate electrode of the second transistor M2 may be connected to a third scan line S3i. The second transistor M2 may be turned on when the third scan signal is supplied to the third scan line S3i, to electrically connect the data line Dj and the first node N1 to each other.” The second scan signal , as disclosed in the specification as filed, is a second scan line S2i.
Applicant may amend the claim to clarify the second transistor turned on in response to the third scan signal, or If applicant wishes to refer for a particular or specific reference character in the figures in reference to a claimed element of the claim, that is different from what is described in the specification, they may do so by including the desired reference character in parenthesis in the claim limitation.
Re Claim 4, recites the limitation “an eighth transistor connected between the third node and a third power line that provides a voltage of a second power source, wherein the eighth transistor is turned on in response to the fifth scan signal.”
Applicant argues “Examiner’s misinterpretation of this language as the eight electrode is turned in response to the fourth scan signal” is unreasonable as conflicting with the remainder of the claim limitations, and necessary resulted in failure to properly examine the claim as written”.
The Examiner disagrees.
The specification as filed describes “[0086] The eighth transistor M8 may be connected between the first electrode of the light emitting element LD (e.g., the fourth node N4) and a fourth power line PL4 which provides the voltage of the third power source Vint2 (hereinafter, referred to as a second initialization power source). In an embodiment, a gate electrode of the eighth transistor M8 may be connected to the fourth scan line S4i.
[0087] The eighth transistor M8 may be turned on when the fourth scan signal is supplied to the fourth scan line S4i, to supply the voltage of the second initialization power source Vint2 to the first electrode of the light emitting element LD.”
Applicant is reminded to maintain the claim language as described in the specification as filed and depicted in the figures as originally filed, in order to avoid confusion and conflicting claim interpretation.
Re Claim 10, recites the limitation “a second transistor connected between the data line and the first node, wherein the second transistor is turned on in response to the second scan signal… wherein the fourth transistor is turned on in response to the first scan signal… a seventh transistor connected between the second node and the first electrode of the light emitting element, wherein the seventh transistor includes a gate electrode connected to the first node.”
Applicant argues “Regarding the Examiners rejections of Claims 10-11, and referring to the embodiment of Applicant's FIG. 6 and corresponding portions of the specification, the Examiner's misinterpretation of this claim language is similarly unreasonable as conflicting with the remainder of the respective claim limitations, and necessarily resulted in failure to properly examine these claims as written”.
The Examiner disagrees.
With respect to Figure 6, the specification as filed describes “[0124] Referring to FIG. 6, a ninth transistor M9 may be turned on based on the fourth scan signal.
[0126] The pixel PXij may include a light emitting element LD, first to ninth transistors M1 to M9, a first capacitor C1, and a second capacitor C2. The light emitting element LD, the first to ninth transistors M1 to M9, and the first capacitor C1, which are shown in FIG. 6, are similar to the light emitting element LD, the first to ninth transistors M1 to M9, and the first capacitor C1, which are shown in FIG. 3, and therefore, for convenience of explanation, a further description of these components and related technical aspects will be omitted.”
With respect to “the second transistor” as claimed, the specification describes: “[0076] The second transistor M2 may be connected between the jth data line Dj (hereinafter, referred to as a data line) and the first node N1. A gate electrode of the second transistor M2 may be connected to a third scan line S3i. The second transistor M2 may be turned on when the third scan signal is supplied to the third scan line S3i, to electrically connect the data line Dj and the first node N1 to each other.”
Thus, the second scan signal , as disclosed in the specification as filed, corresponds a second scan line S2i, not the third scan line as the applicant wishes for the examiner to read as.
With respect to the seventh transistor as claimed, applicant points to Figure 6 in reference to ninth transistor, M9. The specification as filed describes “[0127] The ninth transistor M9 may be connected between a second electrode of the first transistor M1 (e.g., a second node N2) and a first electrode of the light emitting element LD (e.g., a fourth node N4). In an embodiment, a gate electrode of the ninth transistor M9 may be connected to a first node N1.”
However, Claim 11, dependent on Claim 10, recites “an eighth transistor connected between the first electrode of the light emitting element and a third power line that provides a voltage of a second power source, wherein the eighth transistor is turned on in response to the first scan signal”
Applicant points to Figure 6, where it appears that transistor M8 is in reference to the eight transistor as claimed and where fourth scan signal should be read as the first scan signal. There is no such description in the specification as filed.
However, Claim 13, recites “a ninth transistor connected between the third node and a fourth power line that provides a voltage of a third power source, wherein the ninth transistor is turned on in response to the fourth scan signal.”
Applicant points to Figure 6, where it appears that transistor M7 is in reference to the ninth transistor as claimed and where the first scan signal should be read as fourth scan signal. There is no such description in the specification as filed.
Examiner points Applicant to the description of the elements in specification as filed for claim language clarification, in order to avoid confusion and conflicting claim interpretation.
It is further noted, the restriction was withdrawn after further consideration that the differences between the different embodiments were not going to be a burden on the examination, and since as noted in the specification the pixel circuit of Figures 6-7 are similar to that of Figure 3, thus (with the exception of the differences), the description corresponding to Figure 3 also applies to Figures 6-8 where applicable.
Therefore, the 112b rejection is maintained.
Applicant’s arguments, see pages 27-28, filed 01/29/2026, with respect to the rejection(s) of claim(s) 9-11 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made, see above.
Applicant’s arguments, see pages 31-32, filed 01/29/2026, with respect to the rejection(s) of claim(s) 1-8 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made, see above.
Allowable Subject Matter
Claims 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Independent Claim 17 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein a voltage including a plurality of step pulses, each of the plurality of step pulses increasing by a constant step voltage, is provided to a first electrode of the light emitting element before the supply of the emission control signal is suspended” along with the other limitations in the claim.
Claim 8, 10-14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “…supply the second scan signal to the second scan line and supply the third scan signal to the third scan line in the fifth period, and wherein a time at which the fifth period is ended is earlier than a time at which the first period is started” in combination with the other limitations in the claim.
Claim 10 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “a seventh transistor connected between the second node and the first electrode of the light emitting element, wherein the seventh transistor includes a gate electrode connected to the first node” in combination with the other limitations in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
Prosecution Insights