Prosecution Insights
Last updated: April 19, 2026
Application No. 18/966,107

PORT ARBITRATION IN SWITCH NETWORKS FOR DATAFLOW COMPUTER SYSTEMS

Non-Final OA §112
Filed
Dec 02, 2024
Examiner
LEWIS-TAYLOR, DAYTON A.
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Sambanova Systems Inc.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
84%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
568 granted / 701 resolved
+26.0% vs TC avg
Minimal +3% lift
Without
With
+3.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
24 currently pending
Career history
725
Total Applications
across all art units

Statute-Specific Performance

§101
5.7%
-34.3% vs TC avg
§103
50.3%
+10.3% vs TC avg
§102
22.1%
-17.9% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 701 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. Claims 1-20 are pending. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 12/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner. Claim Objections 4. Claim 1 is objected to because of the following informalities: Line 4 states “a switch” and should be replaced with “the switch”. Appropriate correction is required. 5. Claim 4 is objected to because of the following informalities: Line 3 states “a switch” and should be replaced with “the switch”. Appropriate correction is required. 6. Claim 7 is objected to because of the following informalities: Line 1 states “a round robin pointer” and should be replaced with “the round robin pointer”. Appropriate correction is required. 7. Claim 7 is objected to because of the following informalities: Line 3 states “an output port” and should be replaced with “the output port”. Appropriate correction is required. 8. Claim 7 is objected to because of the following informalities: Line 5 states “an output port” and should be replaced with “the output port”. Appropriate correction is required. 9. Claim 8 is objected to because of the following informalities: Line 2 states “a switch” and should be replaced with “the switch”. Appropriate correction is required. 10. Claim 9 is objected to because of the following informalities: Line 3 states “a switch” and should be replaced with “the switch”. Appropriate correction is required. 11. Claim 14 is objected to because of the following informalities: Line 15 states “an output port” and should be replaced with “the output port”. Appropriate correction is required. 12. Claim 18 is objected to because of the following informalities: Line 3 states “an output port” and should be replaced with “the output port”. Appropriate correction is required. 13. Claim 19 is objected to because of the following informalities: Line 3 states “an output port” and should be replaced with “the output port”. Appropriate correction is required. 14. Claim 20 is objected to because of the following informalities: Lines 6-7 state “a switch” and should be replaced with “the switch”. Appropriate correction is required. Claim Rejections - 35 USC § 112 15. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 16. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the switch of source nodes" in line 5. There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites the limitation "the DEoS port metrics" in line 9. There is insufficient antecedent basis for this limitation in the claim. Claim 2 recites the limitation "switches" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 3 recites the limitation "switches" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 5 recites the limitation "the reconfigurable dataflow computer system" in line 1. There is insufficient antecedent basis for this limitation in the claim. Claim 7 recites the limitation "the start of the next arbitration cycle" in line 5. There is insufficient antecedent basis for this limitation in the claim. Claim 8 recites the limitation "the arbiter" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 8 recites the limitation "the relative weights" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 9 recites the limitation "the weight associated with the source node" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 10 recites the limitation "the first set of source nodes" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Claim 10 recites the limitation "the dynamic data input activity" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 10 recites the limitation "the first input port" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. Claim 10 recites the limitation "the port DEoS metric" in lines 8-9. There is insufficient antecedent basis for this limitation in the claim. Claim 13 recites the limitation "the switch of source nodes" in line 5. There is insufficient antecedent basis for this limitation in the claim. Claim 13 recites the limitation "the DEoS port metrics" in line 9. There is insufficient antecedent basis for this limitation in the claim. Claim 16 recites the limitation "switches" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 17 recites the limitation "the first input port" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. Claim 18 recites “the computer-implemented method of 18”. It’s unclear as to what claim should claim 18 depend on. Additional, claim 18 is also incomplete and needs to be fixed. Claim 19 recites the limitation "the start of the next arbitration cycle" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 20 recites the limitation "the arbiter" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 20 recites the limitation "the relative weights" in line 4. There is insufficient antecedent basis for this limitation in the claim. Claim 20 recites the limitation "the weight associated with the source node" in line 6. There is insufficient antecedent basis for this limitation in the claim. Claims 4, 6, 11, 12, 14 and 15 are further rejected based on their dependency of claims 1 and 13. Related Prior Art 17. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. a. Shenbagam et al. (US Patent No. 11,200,096 B1 hereinafter “Shenbagam”) discloses a system is described that has a node and runtime logic. The node has a plurality of processing elements operatively coupled by interconnects. The runtime logic is configured to receive target interconnect bandwidth, target interconnect latency, rated interconnect bandwidth and rated interconnect latency. The runtime logic responds by allocating to configuration files defined by the application graph: (1) processing elements in the plurality of processing elements, and (2) interconnects between the processing elements. The runtime logic further responds by executing the configuration files using the allocated processing elements and the allocated interconnects b. Swarbrick et al. (US Pub. No. 2019/0238453 A1 hereinafter “Swarbrick”) discloses techniques for end-to-end quality-of-service in a network-on-chip. In an example, a method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC. c. Kumar (US Pub. No. 2017/0063697 A1 hereinafter “Kumar”) discloses Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the NoC to compel the acceptance of data and the allocation of an appropriate buffer. Messages sent to the agent may also have a priority associated with the message, wherein higher priority messages have automatic bandwidth allocation and lower priority messages are processed using a handshake protocol. d. Schaffer et al. (US Patent No. 7,395,361 B2 hereinafter “Schaffer”) discloses a bus arbitration algorithm precisely controls the relative bus channel bandwidth allocated to each master device by considering the direction of, and/or the bus channel bandwidth consumed by, a bus transaction. At least one weighting register is associated with each master device; in one embodiment, one weighting register per bus channel. The register is periodically loaded with a proportionate share of the available bus bandwidth. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. In the case of equal initial allocation of relative bandwidth share, master devices that consume bus channel bandwidth will have relatively low priority; master devices that do not consume bus channel bandwidth retain relatively high priority. e. Das et al. (US Pub. No. 2006/0080487 A1 hereinafter “Das”) discloses a PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master. Allowable Subject Matter 18. Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest a switch comprising of a Dynamic Equality of Service (DEoS) arbiter, where the DEoS arbiter maps through-connections to the input ports by arbitrating input ports of the switch (based on dynamic information inputted into the switch of sources), in combination with other recited limitations in independent claims 1 and 13. Dependent claims 2-12 and 14-20 would be allowable based on their dependencies of independent claims 1 and 13. Conclusion The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 2707754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Dayton Lewis-Taylor/ Examiner, Art Unit 2181
Read full office action

Prosecution Timeline

Dec 02, 2024
Application Filed
Feb 21, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12585491
PROCESSING OF INTERRUPTS
2y 5m to grant Granted Mar 24, 2026
Patent 12585610
COMPUTING SYSTEM, PCI DEVICE MANAGER AND INITIALIZATION METHOD THEREOF
2y 5m to grant Granted Mar 24, 2026
Patent 12578901
CLOCK DOMAIN CROSSING
2y 5m to grant Granted Mar 17, 2026
Patent 12572496
HOST FABRIC ADAPTER WITH FABRIC SWITCH
2y 5m to grant Granted Mar 10, 2026
Patent 12572497
DETECTION OF A STUCK DATA LINE OF A SERIAL DATA BUS
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
84%
With Interview (+3.4%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 701 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month