Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1 & 7-9 are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Japanese Publication JP10334672A (published on 12/18/1998, see Google image).
Claims 1 & 20, the prior publication above (see Fig. 2-3 below) already shows a similar inventive concept for a ferroelectric memory device comprising a cell array (see Fig. 1) with a plurality of ferroelectric cells MC, each cell formed at an intersection of the respective crossing word lines WL and bit lines BL, and Fig. 2 further shows that each MC cell has at least one transistor TR coupled to at least one ferroelectric capacitor C capable of storing 2 data bits. Additionally, Fig. 3 further shows that each such capacitor C can also be split further into multiple capacitors (C(1). C(2) … and C(2n-1)), which capable of storing n-bit data (3-bit). Thus, each one of the plurality of memory cells comprises at least one transistor Tr and a plurality of ferroelectric capacitors (2n-1 ferroelectric capacitors) as claimed.
[AltContent: textbox (An integrated/capacitor C can comprises at least 2n-1 ferroelectric capacitors arranged in parallel)][AltContent: arrow][AltContent: textbox (A ferroelectric
memory cell MC)][AltContent: arrow][AltContent: arrow]
PNG
media_image1.png
406
850
media_image1.png
Greyscale
Claim 7, Fig. 3 shows that each of the 2n-1 capacitors are spaced apart and connected as parallel as an integrated capacitor structure (or C of Fig. 2), and each individual capacitor has two opposing electrode plates with an equal size dielectric layer in between, and there are at least 2n-1 capacitors sequentially arranged in a first direction.
Claims 8-9, Fig. 3 shows that each capacitor has equal thickness as well as equal size/length with a same coercive voltage as well.
3. Claims 1 & 7-9 are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Chinese Publication CN1059798A (published on 3/25/1992, see Google image).
Claims 1 & 20, the prior publication above (see Fig. 4-5 below) already shows a similar inventive concept for a ferroelectric memory device comprising a cell array (see Fig. 5, cells 301 to 304 as example) with a plurality of ferroelectric cells MC, each cell formed at an intersection of the respective crossing word lines WL and bit lines BL, and Fig. 4 further shows that each MC cell has at least one transistor 111 coupled to at least four ferroelectric capacitor (112 to 115) capable of storing 2n-1 bit data (for N =2, or 3-bit). Thus, each one of the plurality of memory cells comprises at least one transistor Tr and a plurality of ferroelectric capacitors (2n-1 ferroelectric capacitors) as claimed.
[AltContent: arrow][AltContent: textbox (An integrated/capacitor C can comprises at least 2n-1 ferroelectric capacitors arranged in parallel)]
PNG
media_image2.png
438
500
media_image2.png
Greyscale
[AltContent: arrow]
Claim 7, Fig. 4-5 shows that each of the 2n-1 capacitors are spaced apart and connected as parallel as an integrated capacitor structure (or C of Fig. 2), and each individual capacitor has two opposing electrode plates with an equal size dielectric layer in between, and there are at least 2n-1 capacitors sequentially arranged in a first direction.
Claims 8-9, Fig. 4 shows that each capacitor has equal thickness as well as equal size/length with a same coercive voltage as well.
Allowable Subject Matter
4. The dependent claims 2-6 & 10-20 are objected as being dependent upon the rejected claims above; however, they also tentatively contain other/additional allowable limitations, which are not clearly suggested by the prior arts nor seen elsewhere at this time.
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
Prosecution Insights