DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, 5, 8, and 21-25 have been examined.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to U.S. Provisional Applications filed March 15, 2019.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statements dated December 3, 2024 (x5), February 6, 2025, May 6, 2025, July 14, 2025, September 8, 2025, and November 21, 2025 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. Copies of the PTOL-1449s initialed and dated by the Examiner are attached to the instant office action.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Objections
Claims 5, 23, and 27 are objected to because of the following informalities.
Claim 5 recites, “the elements associated the sparse….” This appears to be a typographical error. Applicant may have intended “the elements associated with the sparse….” Claims 23 and 27 include similar language and are similarly objected to.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 5, 8, and 21-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,842,423 (“reference patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those in the instant application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 8, 21, 22, 24, 25, 26, and 28 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites an apparatus, which falls within the statutory category of machine.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites performing dot product operations. These limitations fall within the “Mental Processes” grouping of abstract ideas as well as the “Mathematical Calculation” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
The claims include additional elements including, processing circuitry, data elements associated with one or more sparse first matrices, the data elements are compacted into a compressed representation representing a non-zero value element and or an indication of the non-zero value element, causing a processing resource associated with the processing circuitry to perform the mathematical calculation on the data elements.
These additional elements do not integrate the judicial exception into a practical application because the additional elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the exception.
Subject Matter Eligibility Analysis Step 2B:
The additional elements are not sufficient to amount to significantly more than the judicial exception. The additional elements include generic computer components and mathematical operations that do not provide an inventive concept. Therefore claim 1 is ineligible.
Claim 2 is dependent upon claim 1 and further recites, “the processing circuitry is further to write output associated with the dot product operation to a memory coupled to the processing circuitry, wherein the memory is further to store the compressed representation in a compressed format, wherein the memory includes a level two cache memory or a shared local memory.”
These additional limitations do not integrate the judicial exception into a practical application because the additional elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the exception. Furthermore, the limitations merely use a computer as a tool to perform the judicial exception. These additional elements are also not sufficient to amount to significantly more than the judicial exception because the additional elements consist of simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception.
Claim 8 is dependent upon claim 1 and further recites, “the sparse first matrix includes weight data associated with a neural network and the second matrix includes input activation data associated with the neural network, and wherein the output associated with the dot product operation includes output activation data associated with the neural network, wherein the sparse first matrix is based on structured sparsity and elements of the sparse first matrix are compacted into the compressed representation based on the structured sparsity.”
These additional limitations do not integrate the judicial exception into a practical application because the additional limitations generally link the use of a judicial exception to a particular technological environment or field of use, which is insufficient to integrate the judicial exception into a practical application. These additional elements are also not sufficient to amount to significantly more than the judicial exception because the additional limitations generally link the use of a judicial exception to a particular technological environment or field of use, which does not amount to significantly more than the judicial exception.
Claims 21, 22, 24, 25, 26, and 28 are corresponding claims. These claims do not include any additional significant limitations with regard to subject matter eligibility and are similarly rejected under § 101 as ineligible.
Claims 25-28 are rejected because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims recite, “At least one computer-readable medium,” which reads on transitory forms of signal transmission. This rejection could be overcome by amending to recite, “At least one non-transitory computer-readable medium.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 5, 8, and 21-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites, “the sparse dot product instruction to cause a processing resource to perform….” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the sparse dot product instruction is to cause a processing resource to perform….” Claims 21 and 25 include similar limitations and are similarly rejected.
Claim 5 recites, “wherein processing resource to perform.” This language is vague and ambiguous. It cannot be determined whether the claim refers to the same processing resource as introduced in claim 1 or a different processing resource For purposes of examination, this limitation is interpreted as, “wherein the processing resource is to perform.”
Claim 5 recites, “the processing resources.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the processing resource[[s]].” Claims 23 and 27 include similar limitations and are similarly rejected.
Claim 5 recites, “the elements.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the data elements.” Claims 23 and 27 include similar limitations and are similarly rejected.
Claim 5 recites, “the internal memory.” There is insufficient antecedent basis for this limitation in the claim. Claims 23 and 27 include similar limitations and are similarly rejected.
Claim 5 recites, “the compressed representation loaded from the memory.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the compressed representation is loaded from the memory.” Claims 23 and 27 include similar limitations and are similarly rejected.
Claim 8 recites, “the second matrix.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the sparse second matrix.” Claims 24 and 28 include similar limitations and are similarly rejected.
Claim 8 recites, “the output associated with the dot product operation.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “[[the]] output associated with the dot product operation.” Claims 24 and 28 include similar limitations and are similarly rejected.
Claims 2, 5, 8, 22-24, and 26-28 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 21, 22, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2017/0090924 by Mishra et al. (previously cited and hereinafter referred to as “Mishra).
Regarding claims 1, 21, and 25, taking claim 1 as representative, Mishra discloses:
an apparatus comprising: processing circuitry to: (Mishra discloses, at Figure 3 and related description, a processor, i.e., an apparatus, comprising an execution unit, i.e. processing circuitry. Mishra also discloses, at ¶ [0233], an embodiment using instructions stored on machine-readable media.):
perform a dot product operation on data elements associated with one or more of a sparse first matrix or a sparse second matrix in response to a sparse dot product…[algorithm], wherein the data elements associated with the sparse first matrix are compacted into a compressed representation representing a non-zero value element or an indication of the non-zero value element, wherein the sparse dot product …[algorithm] to cause a processing resource associated with the processing circuitry to perform the dot product operation on the data elements (Mishra discloses, at ¶ [0035] et seq., performing dot product operations on data elements from sparse matrices. As disclosed at ¶ [0033], the elements can be represented in a compressed format that indicates the non-zero elements. As disclosed at ¶ [0060], the dot product operations are performed as an algorithm to accelerate arithmetic, which discloses causing resources of the execution unit, i.e., a processing resource associated with the processing circuitry, to perform the dot product operation.).
Mishra does not explicitly disclose performing the sparse dot product algorithm in response to a sparse dot product instruction. However, Mishra discloses performing operations in response to instructions. See, e.g., ¶ [0059]. It would have been obvious to modify Mishra to include a sparse dot product instruction because implementing algorithms in response to corresponding instructions improves performance by reducing the amount of code needed to perform the algorithms.
Regarding claims 2, 22, and 26, taking claim 2 as representative, Mishra, as modified, discloses the elements of claim 1, as discussed above. Mishra also discloses:
the processing circuitry is further to write output associated with the dot product operation to a memory coupled to the processing circuitry, wherein the memory is further to store the compressed representation in a compressed format, wherein the memory includes a level two cache memory or a shared local memory (Mishra discloses, at ¶ [0060], performing dot product operations, which discloses writing output to memory. As disclosed at ¶ [0046], the compressed representation can also be stored in memory. As disclosed at ¶ [0197], the memory can be L2 cache.).
Claims 5, 23, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of US Publication No. 2019/0114534 by Teng et al. (previously cited and hereinafter referred to as “Teng”).
Regarding claims 5, 23, and 27, taking claim 5 as representative, Mishra, as modified, discloses the elements of claim 1, as discussed above. Mishra also discloses:
processing resource to perform the dot product operation via a matrix accelerator, wherein the matrix accelerator is configured to select one or more of the elements associated the sparse second matrix from a vector in the internal memory based on the indication of the non-zero value element, wherein the compressed representation loaded from the memory into an internal memory within the processing resources, the internal memory having a register file or a level one cache memory … (Mishra discloses, at ¶ [0060], performing dot product operations. As disclosed at ¶ [0226], operations can be performed by accelerators, which discloses a matrix accelerator. As disclosed at Figure 3 and related description, the elements are loaded from memory such as registers, which discloses internal memory. As disclosed at Figure 2 and related description, the elements are selected based on indications of non-zero elements.).
Mishra does not explicitly disclose the matrix accelerator comprises a systolic array of processing resources.
However, in the same field of endeavor (e.g., neural networks) Teng discloses:
systolic arrays (Teng discloses, at ¶ [0054], systolic arrays.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra to include a systolic array, as disclosed by Teng, in order to improve performance by utilizing an efficient architecture for parallel processing.
Claims 8, 24, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Teng in view of US Publication No. 2021/0012197 by Simonyan et al. (previously cited and hereinafter referred to as “Simonyan”).
Regarding claims 8, 24, and 28, taking claim 8 as representative, Mishra, as modified, discloses the elements of claim 1, as discussed above. Mishra does not explicitly disclose the sparse first matrix includes weight data associated with a neural network and the second matrix includes input activation data associated with the neural network, and wherein the output associated with the dot product operation includes output activation data associated with the neural network, wherein the sparse first matrix is based on structured sparsity and elements of the sparse first matrix are compacted into the compressed representation based on the structured sparsity.
However, in the same field of endeavor (e.g., neural networks) Teng discloses:
weight data associated with a neural network and input activation data associated with the neural network output activation data associated with the neural network (Teng discloses, at ¶ [0043], weight and activation data associated with a neural network.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra to include weight and activation data, as disclosed by Teng, in order to implement a neural network.
Also in the same field of endeavor (e.g., matrix multiplication) Simonyan discloses:
structured sparsity and elements are compacted into the compressed representation based on the structured sparsity (Simonyan discloses, at ¶ [0042], clearing values of blocks according to a predefined sparsity pattern, which discloses structured sparsity and pruning to a predetermined pattern that includes at least one zero value element and at least one non-zero value element.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra to utilize a structured sparsity, as disclosed by Simonyan, in order to improve performance by reducing data storage requirements. See Simonyan, ¶ [0009].
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 11836497 by Wang discloses compressed representation, sparse data, dot product instruction.
US 20200159810 by Ghosh discloses compressed representation, sparse data, dot product.
US 20200104692 by Hill discloses compressed representation, sparse data, dot product.
US 20160179574 by Merrill discloses compressed representation, sparse data, dot product.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAWN DOMAN/Primary Examiner, Art Unit 2183