DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, 5, 8, and 21-28 have been amended.
Claims 1, 2, 5, 8, and 21-28 have been examined.
The specification and claim objections in the previous Office Action have been addressed and are withdrawn.
The § 101 and double patenting rejections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Information Disclosure Statement
The applicant's submission of the Information Disclosure Statements dated February 3, 2026 and April 6, 2026 (x2) is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. Copies of the PTOL-1449s initialed and dated by the examiner are attached to the instant office action.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 5, 8, and 21-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,842,423 (“reference patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those in the instant application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 8, 21, 22, 24, 25, 26, and 28 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites an apparatus, which falls within the statutory category of machine.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites performing dot product operations. These limitations fall within the “Mental Processes” grouping of abstract ideas as well as the “Mathematical Calculation” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
The claims include additional elements including, processing circuitry, data elements associated with one or more sparse first matrices, the data elements are compacted into a compressed representation representing a non-zero value element and or an indication of the non-zero value element, causing a processing resource associated with the processing circuitry to perform the mathematical calculation on the data elements.
These additional elements do not integrate the judicial exception into a practical application because the additional elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the exception.
Subject Matter Eligibility Analysis Step 2B:
The additional elements are not sufficient to amount to significantly more than the judicial exception. The additional elements include generic computer components and mathematical operations that do not provide an inventive concept. Therefore claim 1 is ineligible.
Claim 2 is dependent upon claim 1 and further recites, “the processing circuitry is further to write output associated with the dot product operation to a memory coupled to the processing circuitry, wherein the memory is further to store the compressed representation in a compressed format, wherein the memory includes a level two cache memory or a shared local memory, wherein the compressed representation further represents an indication of the non-zero value element.”
These additional limitations do not integrate the judicial exception into a practical application because the additional elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the exception. Furthermore, the limitations merely use a computer as a tool to perform the judicial exception. These additional elements are also not sufficient to amount to significantly more than the judicial exception because the additional elements consist of simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception.
Claim 8 is dependent upon claim 1 and further recites, “the sparse first matrix includes weight data associated with a neural network and the second matrix includes input activation data associated with the neural network, and wherein the output associated with the dot product operation includes output activation data associated with the neural network, wherein the sparse first matrix is based on structured sparsity and elements of the sparse first matrix are compacted into the compressed representation based on the structured sparsity, wherein the processing circuitry comprises graphics processing circuitry.”
These additional limitations do not integrate the judicial exception into a practical application because the additional limitations generally link the use of a judicial exception to a particular technological environment or field of use, which is insufficient to integrate the judicial exception into a practical application. These additional elements are also not sufficient to amount to significantly more than the judicial exception because the additional limitations generally link the use of a judicial exception to a particular technological environment or field of use, which does not amount to significantly more than the judicial exception.
Claims 21, 22, 24, 25, 26, and 28 are corresponding claims. These claims do not include any additional significant limitations with regard to subject matter eligibility and are similarly rejected under § 101 as ineligible.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 23, and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites, “the compressed representation further represents an indication of the non-zero value element.” This term is vague and ambiguous, rendering the scope of the claims indefinite. It cannot be definitely determined what it means to represent an indication of a non-zero element. What is involved in this representation. For purposes of examination, the limitation is interpreted as, “the compressed representation includes an indication of the non-zero value element.” This is based on, e.g., ¶ [0465] of the specification as filed, which recites, “a compressed representation including a set of elements, the set of elements including at least one non-zero value element and an indication of the at least one non-zero value element.” Claims 22 and 26 include similar limitations and are similarly rejected.
Claim 5 recites, “the internal memory.” There is insufficient antecedent basis for this limitation in the claim. Claims 23 and 27 include similar limitations and are similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 21, 22, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2017/0090924 by Mishra et al. (previously cited and hereinafter referred to as “Mishra).
Regarding claims 1, 21, and 25, taking claim 1 as representative, Mishra discloses:
an apparatus comprising: processing circuitry to: (Mishra discloses, at Figure 3 and related description, a processor, i.e., an apparatus, comprising an execution unit, i.e. processing circuitry. Mishra also discloses, at ¶ [0233], an embodiment using instructions stored on machine-readable media.):
perform a dot product operation on data elements associated with a sparse first matrix or a sparse second matrix in response to a sparse dot product…[algorithm], wherein the data elements associated with the sparse first matrix are compacted into a compressed representation representing a non-zero value element, wherein the sparse dot product …[algorithm] is to cause a processing resource associated with the processing circuitry to perform the dot product operation on the data elements (Mishra discloses, at ¶ [0035] et seq., performing dot product operations on data elements from sparse matrices. As disclosed at ¶ [0033], the elements can be represented in a compressed format that indicates the non-zero elements. As disclosed at ¶ [0060], the dot product operations are performed as an algorithm to accelerate arithmetic, which discloses causing resources of the execution unit, i.e., a processing resource associated with the processing circuitry, to perform the dot product operation.).
Mishra does not explicitly disclose performing the sparse dot product algorithm in response to a sparse dot product instruction. However, Mishra discloses performing operations in response to instructions. See, e.g., ¶ [0059]. It would have been obvious to modify Mishra to include a sparse dot product instruction because implementing algorithms in response to corresponding instructions improves performance by reducing the amount of code needed to perform the algorithms.
Regarding claims 2, 22, and 26, taking claim 2 as representative, Mishra, as modified, discloses the elements of claim 1, as discussed above. Mishra also discloses:
the processing circuitry is further to write output associated with the dot product operation to a memory coupled to the processing circuitry, wherein the memory is further to store the compressed representation in a compressed format, wherein the memory includes a level two cache memory or a shared local memory, wherein the compressed representation further represents an indication of the non-zero value element. (Mishra discloses, at ¶ [0060], performing dot product operations, which discloses writing output to memory. As disclosed at ¶ [0046], the compressed representation can also be stored in memory. As disclosed at ¶ [0197], the memory can be L2 cache. As disclosed at Figure 2 and related description, the compressed representation can be CRS, which includes the element values and an index, i.e., indication, of the non-zero values.).
Claims 5, 23, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of US Publication No. 2019/0114534 by Teng et al. (previously cited and hereinafter referred to as “Teng”).
Regarding claims 5, 23, and 27, taking claim 5 as representative, Mishra, as modified, discloses the elements of claim 1, as discussed above. Mishra also discloses:
the processing resource is to perform the dot product operation via a matrix accelerator, wherein the matrix accelerator is configured to select one or more of the data elements associated with the sparse second matrix from a vector in the internal memory based on the indication of the non-zero value element, wherein the compressed representation is loaded from the memory into an internal memory within the processing resource, the internal memory having a register file or a level one cache memory … (Mishra discloses, at ¶ [0060], performing dot product operations. As disclosed at ¶ [0226], operations can be performed by accelerators, which discloses a matrix accelerator. As disclosed at Figure 3 and related description, the elements are loaded from memory such as registers, which discloses internal memory. As disclosed at Figure 2 and related description, the elements are selected based on indications of non-zero elements.).
Mishra does not explicitly disclose the matrix accelerator comprises a systolic array of processing resources.
However, in the same field of endeavor (e.g., neural networks) Teng discloses:
systolic arrays (Teng discloses, at ¶ [0054], systolic arrays.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra to include a systolic array, as disclosed by Teng, in order to improve performance by utilizing an efficient architecture for parallel processing.
Claims 8, 24, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Teng in view of US Publication No. 2021/0012197 by Simonyan et al. (previously cited and hereinafter referred to as “Simonyan”).
Regarding claims 8, 24, and 28, taking claim 8 as representative, Mishra, as modified, discloses the elements of claim 1, as discussed above. Mishra also discloses:
the processing circuitry comprises graphics processing circuitry (Mishra discloses, at ¶ [0045], graphics circuitry.).
Mishra does not explicitly disclose the sparse first matrix includes weight data associated with a neural network and the sparse second matrix includes input activation data associated with the neural network, and wherein an output associated with the dot product operation includes output activation data associated with the neural network, wherein the sparse first matrix is based on structured sparsity and elements of the sparse first matrix are compacted into the compressed representation based on the structured sparsity.
However, in the same field of endeavor (e.g., neural networks) Teng discloses:
weight data associated with a neural network and input activation data associated with the neural network output activation data associated with the neural network (Teng discloses, at ¶ [0043], weight and activation data associated with a neural network.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra to include weight and activation data, as disclosed by Teng, in order to implement a neural network.
Also in the same field of endeavor (e.g., matrix multiplication) Simonyan discloses:
structured sparsity and elements are compacted into the compressed representation based on the structured sparsity (Simonyan discloses, at ¶ [0042], clearing values of blocks according to a predefined sparsity pattern, which discloses structured sparsity and pruning to a predetermined pattern that includes at least one zero value element and at least one non-zero value element.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra to utilize a structured sparsity, as disclosed by Simonyan, in order to improve performance by reducing data storage requirements. See Simonyan, ¶ [0009].
Response to Arguments
On page 10 of the response filed May 7, 2026 (“response”), the Applicant argues, “Applicant would timely submit a terminal disclaimer at the time of allowance of the pending claims, provided this double patenting rejection remains outstanding at the time of allowance.”
The Applicant’s remarks are essentially a request to hold the double patenting rejection in abeyance, which is improper. MPEP § 804.1(B)(1) states, “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance…. Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only compliance with objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner.” In the interest of compact prosecution, the Examiner will consider the Applicant’s reply as adequate, rather than requiring a complete reply at this point.
On pages 10-12 of the response the Applicant argues that the § 101 rejection should be withdrawn for a number of reasons, including: “Applicant respectfully disagrees with the Examiner's characterization and submits that it overgeneralizes the claims and omits the claim language that defines the claimed advance, such as execution of a sparse dot product instruction by processing circuitry/processor hardware on data elements compacted into a compressed representation that represents a non-zero value element as recited by claim 1;” “the pending claims are not directed to a mental process. A human mind does not fetch, decode, or execute a machine-level sparse dot product instruction that causes a processing resource associated with processing circuitry or a processor to operate on a machine-readable compressed representation of sparse matrix data;” “Even assuming, for argument's sake only, that the claims involve mathematical operations, the claims integrate any such operation into a practical application under Step 2A, Prong Two. The claimed sparse dot product instruction and compressed representation improve sparse workload processing by reducing the amount of data transmitted or stored and by enabling zero-skipping and selective operation on relevant sparse matrix elements. The Specification describes sparse neural network data encoded in a reduced-bit format, with a header and significance map identifying non-zero values, to reduce data required to be transmitted or stored. See Specification, paragraph 0377;” and “The Examiner's conclusion that the additional elements are merely generic computer components also overlooks the disclosed and claimed hardware implementation. The Specification describes systolic arrays configured for matrix dot product operations and explains that communication bandwidth within processing resources may be preserved by locating communication traffic among systolic arrays, cache/shared local memory, and shared register files. See Specification, paragraphs 0380-0382.”
Though fully considered, the Examiner respectfully disagrees. All of these arguments rely upon features from the specification, not the claims. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 13 of the response the Applicant argues , “claim 1 proposes instruction-level relationship and that comparison-and-mask functionality is not the same as a sparse dot product instruction that triggers performance of a dot product operation on data elements associated with a compacted sparse representation as recited by claim 1.”
Though fully considered, the Examiner respectfully disagrees. As noted above, Mishra discloses CSR, which omits zero, and performing sparse dot product operations. The Examiner acknowledges Mishra does not teach a single instruction that causes the dot product operations to be performed. However, the Examiner maintains that it is fundamentally well-known to encode instructions to perform operations. Therefore, it would have been obvious to modify Mishra to include a dot product instruction for performing the sparse dot product operations. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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