DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 10-13 and 15-18 of U.S. Patent No. 11,087,819. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-3, 5-8, 11-19 are anticipated by claims 1-3, 10-13 and 15-18 of the patent and claims 4, 9, 10 and 20 would have been obvious over claims 10, 13, 18, 19 and 21 of the patent.
Regarding claim 1, claims 10, 13 and 18 of the patent recite a dynamic random access memory (DRAM) device, comprising:
one or more banks (claim 13); and
processing circuitry coupled with the one or more banks and configured to cause the DRAM device to:
identify an activation command issued to a bank of the one or more banks (claim 10, lines 4-5, the number of activations must be associated with at least one activation command):
modify (determine and decrease), in response to the activation command, a count associated with the bank; and
perform (execute) refresh management for the bank based at least in part on determining that the count satisfies a threshold (claim 10, lines 6-7).
Regarding claim 2, claim 11 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
enable refresh management operations (the first and second refresh management operations), wherein performing the refresh management is based at least in part on enabling the refresh management operations.
Regarding claim 3, claim 12 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
disable (disallow) refresh management operations after performing the refresh management.
Regarding claim 4, Claim 11 of the patent recites the DRAM device of claim 1, wherein a value of the threshold is stored in a register of the DRAM device, the threshold comprising an initial management threshold (the first predetermined threshold).
It would have been obvious to one having ordinary skill in the art to use a register to store a value of the threshold (the first predetermined threshold).
Regarding claim 5, claim 10 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to: decrease, in response to performance of the refresh management, the count by a quantity that is based on the threshold (claim 10, lines 9-11).
Regarding claim 6, claim 10 of the patent recites the DRAM device of claim 5, wherein the quantity is equal to the threshold (claim 10, lines 9-10).
Regarding claim 7, claims 10,15 and 17 of the patent recite the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
decrease, in response to performance of the refresh management, a plurality of counts associated with each bank of a plurality of banks of the DRAM device, each count of the plurality of counts decreased by a quantity that is based at least in part on the threshold.
Regarding claim 8, claim 12 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
disallow one or more additional activation commands associated with the bank in response to the count exceeding a maximum value.
Regarding claims 9 and 10, it would have been obvious to one having ordinary skill in the art to recognize that the apparatus of claims 9 and 10 and the DRAM device of claims 10 and 12 of the patent are identical in structure; therefore, the differences between claims 9 and 10 of the instant application and claims 10 and 12 of the patent are only functional limitations.
Regarding claim 11, claims 10, 15 and16 of the patent recite the DRAM device of claim 8, wherein the processing circuitry is further configured to cause the DRAM device
issue periodic refresh commands associated with the bank; and
decrease, in response to issuing a refresh command of the periodic refresh commands, the count associated with the bank by a quantity that is based on the threshold.
Regarding claim 12, claims 10, 15 and 17 of the patent recite the. The DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue, in response to the count exceeding the threshold, a refresh management all bank command for a plurality of banks of the DRAM device, the plurality of banks comprising the bank, wherein performance of the refresh management is based at least in part on the refresh management all bank command.
Regarding claim 13, claims 10, 15 and 16 of the patent recite the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM
issue, in response to the count exceeding the threshold, a refresh management same bank command for the bank of the DRAM device, wherein performance of the refresh management is based at least in part on the refresh management same bank command.
Regarding claim 14, claim 1 of the patent recites a method, comprising:
identifying an activation command issued to a bank of one or more banks of a dynamic random access memory (DRAM) device (it would have been obvious to one having ordinary skill in the art to recognize that an activation command must be issued to a bank (claim 4) of a DRAM in order to perform a number of activations):
modifying, in response to the activation command, a count associated with the bank (determining and decreasing a count); and
performing refresh management for the bank based on determining that the count satisfies a threshold (scheduling a refresh management operation and executing the scheduled refresh management operation in response to the count exceeding a first predetermined threshold).
Regarding claim 15, claims 1 and 2 recite the method of claim 14, further
enabling refresh management operations, wherein performing the refresh management is based at least in part on enabling the refresh management operations.
Regarding claim 16, claim 1 and 3 recite the method of claim 14, further
comprising:
disabling refresh management operations after performing the refresh management.
Regarding claim 17, claims 1 and 2 of the patent recites the method of claim 14, wherein a value of the threshold is stored in a register of the DRAM device, the threshold comprising an initial management threshold.
It would have been obvious to one having ordinary skill in the art to use a register to store a value of the threshold (the first predetermined threshold).
Regarding claim 18, claim 1 of the patent recites the method of claim 14,
decreasing, in response to performance of the refresh management, the count by a quantity that is based on the threshold.
Regarding claim 19, claim 1 of the patent recites the method of claim 18, wherein the quantity is equal to the threshold.
Regarding claim 20, it would have been obvious to one having ordinary skill in the art to recognize that the memory system of claim 20 of the instant application and the apparatus of claims 19 and 21 of the patent are identical in structure; therefore the differences between claim 20 and claims 19 and 21 are only functional limitations.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 9-11 and 13-16 of U.S. Patent No. US 11,810,610. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-5, 7, 8 and 11-19 are anticipated by claims 1, 2, 9-11 and 13-16 of the patent and claims 6, 9, 10 and 20 would have been obvious over claims 9, 11 and 16 of the patent.
Regarding claim 1, claims 9, 11 and 16 of the patent recite a dynamic random access memory (DRAM) device, comprising:
one or more banks (claim 11); and
processing circuitry coupled with the one or more banks and configured to cause the DRAM device to:
identify an activation command (claim 9, line 6) issued to a bank of the one or more banks (claim 9, lines 4-5, the number of activations must be associated with at least one activation command):
modify (determine), in response to the activation command, a count associated with the bank; and
perform (execute) refresh management for the bank based at least in part on determining that the count satisfies a threshold (claim 9, lines 6-8).
Regarding claim 2, claim 9, 11 and 16 of the patent recite the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
enable refresh management operations (the first and second refresh management operations), wherein performing the refresh management is based at least in part on enabling the refresh management operations.
Regarding claim 3, claim 10 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
disable (disallow) refresh management operations after performing the refresh management.
Regarding claim 4, Claim 9 of the patent recites the DRAM device of claim 1, wherein a value of the threshold is stored in a register of the DRAM device, the threshold comprising an initial management threshold (the first predetermined threshold).
It would have been obvious to one having ordinary skill in the art to use a register to store a value of the threshold (the first predetermined threshold).
Regarding claim 5, claim 9 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
decrease, in response to performance of the refresh management, the count by a quantity that is based on the threshold (claim 9, lines 9-10).
Regarding claim 7, claims 9, 13 and 15 of the patent recite the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
decrease, in response to performance of the refresh management, a plurality of counts associated with each bank of a plurality of banks of the DRAM device, each count of the plurality of counts decreased by a quantity that is based at least in part on the threshold.
Regarding claim 8, claim 10 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
disallow one or more additional activation commands associated with the bank in response to the count exceeding a maximum value.
Regarding claims 6, 9 and 10, it would have been obvious to one having ordinary skill in the art to recognize that the apparatus of claims 6, 9 and 10 and the DRAM device of claims 9 and 10 of the patent are identical in structure; therefore, the differences between claims 9 and 10 of the instant application and claims 9 and 10 of the patent are only functional limitations.
Regarding claim 11, claims 9, 13 and14 of the patent recite the DRAM device of claim 8, wherein the processing circuitry is further configured to cause the DRAM device
issue periodic refresh commands associated with the bank; and
decrease, in response to issuing a refresh command of the periodic refresh commands, the count associated with the bank by a quantity that is based on the threshold.
Regarding claim 12, claims 9, 13 and 15 of the patent recite the. The DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue, in response to the count exceeding the threshold, a refresh management all bank command for a plurality of banks of the DRAM device, the plurality of banks comprising the bank, wherein performance of the refresh management is based at least in part on the refresh management all bank command.
Regarding claim 13, claims 9 and 11 of the patent recite the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM
issue, in response to the count exceeding the threshold, a refresh management same bank command for the bank of the DRAM device, wherein performance of the refresh management is based at least in part on the refresh management same bank command.
Regarding claim 14, claim 1 of the patent recites a method, comprising:
identifying an activation command (claim 1, line 4) issued to a bank of one or more banks of a dynamic random access memory (DRAM) device (it would have been obvious to one having ordinary skill in the art to recognize that an activation command must be issued to a bank (claim 3) of a DRAM in order to perform a number of activations):
modifying (determining), in response to the activation command, a count associated with the bank; and
performing refresh management for the bank based on determining that the count satisfies a threshold (claim 1, lines 4-6).
Regarding claim 15, claims 1 and 2 recite the. The method of claim 14, further
enabling refresh management operations, wherein performing the refresh management is based at least in part on enabling the refresh management operations.
Regarding claim 16, claim 1 and 2 of the patent recite the method of claim 14, further comprising:
disabling refresh management operations after performing the refresh management.
Regarding claim 17, claim 1 of the patent recites the method of claim 14, wherein a value of the threshold is stored in a register of the DRAM device, the threshold comprising an initial management threshold.
It would have been obvious to one having ordinary skill in the art to use a register to store a value of the threshold (the first predetermined threshold).
Regarding claim 18, claim 1 of the patent recites the method of claim 14,
decreasing, in response to performance of the refresh management, the count by a quantity that is based on the threshold.
Regarding claim 19, claim 1 of the patent recites the method of claim 18, wherein the quantity is equal to the threshold.
Regarding claim 20, it would have been obvious to one having ordinary skill in the art to recognize that the memory system of claim 20 of the instant application and the apparatus of claims 9, 11 and 16 of the patent are identical in structure; therefore the differences between claim 20 and claims 9, 11 and 16 are only functional limitations.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4, 5, 10, 11, 19-22, 24-27 and 29-31 of U.S. Patent No. 12,183,383. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 4-14 and 17-20 are anticipated by claims 4, 5, 10, 11, 19-22, 24-27 and 29-31 and claims 2, 3, 14 and 15 would have been obvious over claim 19
Regarding claim 1, claim 19 of the patent recites a dynamic random access memory (DRAM) device, comprising:
one or more banks (claim 19, line 5); and
processing circuitry (controller) coupled with the one or more banks and configured to cause the DRAM device to:
identify an activation command issued to a bank of the one or more banks (claim 19, line 5):
modify (increase), in response to the activation command, a count associated with the bank; and
perform refresh management for the bank based at least in part on determining that the count satisfies a threshold (claim 19, lines 11-13, it is inherent that the controller performs the refresh management after receiving the refresh management command).
Regarding claims 2 and 3, it would have been obvious to one having ordinary skill in the art to recognize that the DRAM device of claims 2 and 3 of the instant application and the memory system of claim 19 of the patent are identical in structure; therefore, the differences between claims 2 and 3 and claim 19 of the patent are only functional limitations.
Regarding claim 4, Claim 20 of the patent recites the DRAM device of claim 1, wherein a value of the threshold is stored in a register of the DRAM device, the threshold comprising an initial management threshold.
Regarding claim 5, claim 25 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
decrease, in response to performance of the refresh management, the count by a quantity that is based on the threshold.
Regarding claim 6, claim 26 of the patent recites the DRAM device of claim 5, wherein the quantity is equal to the threshold (claim 10, lines 9-10).
Regarding claim 7, claim 27 of the patent recite the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
decrease, in response to performance of the refresh management, a plurality of counts associated with each bank of a plurality of banks of the DRAM device, each count of the plurality of counts decreased by a quantity that is based at least in part on the threshold.
Regarding claim 8, claim 21 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
disallow one or more additional activation commands associated with the bank in response to the count exceeding a maximum value.
Regarding claim 9, claim 22 of the patent recites the DRAM device of claim 8, wherein the processing circuitry is further configured to cause the DRAM device to:
permit the one or more additional activation commands associated with the bank in response to the count dropping below the maximum value after performance of the refresh management.
Regarding claim 10, claim 24 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
permit one or more additional activation commands associated with the bank in response to the count being less than a maximum value.
Regarding claim 11, claim 29 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue periodic refresh commands associated with the bank; and
decrease, in response to issuing a refresh command of the periodic refresh commands, the count associated with the bank by a quantity that is based on the threshold.
Regarding claim 12, claim 30 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue, in response to the count exceeding the threshold, a refresh management all bank command for a plurality of banks of the DRAM device, the plurality of banks comprising the bank, wherein performance of the refresh management is based at least in part on the refresh management all bank command.
Regarding claim 13, claim 31 of the patent recites the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue, in response to the count exceeding the threshold, a refresh management same bank command for the bank of the DRAM device, wherein performance of the refresh management is based at least in part on the refresh management same bank command.
Regarding claim 14, claim 4 of the patent recite a method, comprising:
identifying (monitoring) an activation command issued to a bank of one or more banks of a dynamic random access memory (DRAM) device:
modifying (incrementing), in response to the activation command, a count associated with the bank; and
performing (issuing a refresh management command to perform refresh management) refresh management for the bank based on determining that the count satisfies a threshold.
Regarding claims 15 and 16, it would have been obvious to one having ordinary skill in the art to recognize that the memory system of claim 19 of the patent can be used to perform the method of claims 15 and 16.
Regarding claim 17, claim 5 of the patent recites the method of claim 14, wherein a value of the threshold is stored in a register of the DRAM device, the threshold comprising an initial management threshold.
Regarding claim 18, claim 10 of the patent recites the method of claim 14, further comprising:
decreasing, in response to performance of the refresh management, the count by a quantity that is based on the threshold.
Regarding claim 19, claim 11 of the patent recites the method of claim 18, wherein the quantity is equal to the threshold.
Regarding claim 20, claim 19 of the patent recites a memory system, comprising:
a dynamic random access memory (DRAM) device; and
a controller coupled with the DRAM device and operable to:
increase a count associated with a bank of the DRAM device in response to one or more activation commands issued to the bank; and
issue a refresh management command for the bank in response to the count exceeding a threshold, and
wherein the DRAM device is operable to:
perform refresh management for the bank in response to the refresh management command and in response to a quantity of the one or more activation commands.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hughes et al. (US 10,446,215, hereinafter “Hughes”).
Regarding claims 1, 14 and 20, Hughes discloses a dynamic random access memory (DRAM) device, a method and a memory system comprising:
one or more banks (column 4, lines 64-67); and
processing circuitry (Fig. 1, 1) coupled with the one or more banks and configured to cause the DRAM device to:
identify an activation command issued to a bank of the one or more banks (column 5, lines 39-44):
modify, in response to the activation command, a count associated with the bank; and
perform refresh management for the bank based at least in part on determining that the count satisfies a threshold (column 11, lines 48-60).
Regarding claims 2 and 15, Hughes discloses the DRAM device of claim 1 and the method of claim 14, wherein the processing circuitry is further configured to cause the DRAM device to:
enable refresh management operations, wherein performing the refresh management is based at least in part on enabling the refresh management operations (Abstract, lines 10-13).
Regarding claims 3 and 16, Hughes discloses the DRAM device of claim 1 and the method of claim 14, wherein the processing circuitry is further configured to cause the DRAM device to:
disable refresh management operations after performing the refresh management (column 16, lines 35-38).
Regarding claims 4 and 17, Hughes discloses the DRAM device of claim 1 and the method of claim 14, wherein a value of the threshold is stored in a register of the DRAM device, the threshold comprising an initial management threshold (column 11, lines 45-46).
Regarding claims 5 and 18, Hughes discloses the DRAM device of claim 1 and the method of claim 14, wherein the processing circuitry is further configured to cause the DRAM device to:
decrease, in response to performance of the refresh management, the count by a quantity that is based on the threshold (column 18, lines 16-19).
Regarding claims 6 and 19, Hughes discloses the DRAM device of claim 5 and the method of claim 18, wherein the quantity is equal to the threshold (column 18, lines 16-19, Threshold based measure).
Regarding claim 7, Hughes discloses the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
decrease, in response to performance of the refresh management, a plurality of counts associated with each bank of a plurality of banks of the DRAM device, each count of the plurality of counts decreased by a quantity that is based at least in part on the threshold (column 13, lines 38-40).
Regarding claim 8, Hughes discloses the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
disallow one or more additional activation commands associated with the bank in response to the count exceeding a maximum value (column 13, lines 40-44).
Regarding claim 9, Hughes discloses the DRAM device of claim 8, wherein the processing circuitry is further configured to cause the DRAM device to: permit the one or more additional activation commands associated with the bank in response to the count dropping below the maximum value after performance of the refresh management (column 18, lines 48-53).
Regarding claim 10, Hughes discloses the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
permit one or more additional activation commands associated with the bank in response to the count being less than a maximum value (column 18, lines 48-53).
Regarding claim 11, Hughes discloses the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue periodic refresh commands (column 4, line 64-67, Periodically scheduled refresh operations require periodic refresh commands) associated with the bank; and
decrease, in response to issuing a refresh command of the periodic refresh commands, the count associated with the bank by a quantity that is based on the threshold (column 18, lines 14-19).
Regarding claim 12, Hughes discloses the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue, in response to the count exceeding the threshold, a refresh management all bank command for a plurality of banks of the DRAM device, the plurality of banks comprising the bank, wherein performance of the refresh management is based at least in part on the refresh management all bank command (column 11, lines 48-60).
Regarding claim 13, Hughes discloses the DRAM device of claim 1, wherein the processing circuitry is further configured to cause the DRAM device to:
issue, in response to the count exceeding the threshold, a refresh management same bank command for the bank of the DRAM device, wherein performance of the refresh management is based at least in part on the refresh management same bank command (column 4, lines 15-19).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUAN HOANG/ Primary Examiner, Art Unit 2827
Prosecution Insights