DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No.12,198,767. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-19 would have been obvious .
Regarding claim 1, claim 1 of the patent recites a memory system comprising:
a semiconductor memory device; and
a memory controller (claim 1, line 11),
wherein:
the semiconductor memory device includes:
a first plane including a plurality of first blocks, each of the first blocks including a first memory cell;
a second plane including a plurality of second blocks, each of the second blocks including a second memory cell;
a voltage generator which includes a first driver configured to supply power to the first plane and a second driver configured to supply power to the second plane;
an input/output circuit configured to receive a command set from the memory controller; and
a sequencer configured to execute an operation in response to the command set,
the memory controller is configured to send the command set to the semiconductor memory device,
when the memory controller sends a first command set that instructs execution of a first operation to the first memory cell of one of the first blocks, the sequencer of the semiconductor memory device executes the first operation, the first operation causing a change of a threshold voltage of the first memory cell of the one of the first blocks,
when the memory controller sends a second command set that instructs execution of a second operation to the second memory cell of one of the second blocks during execution of the first operation, the sequencer of the semiconductor memory device executes the second operation in parallel with the first operation, and
when the memory controller sends a third command set that instructs execution of a third operation to the first memory cell of another one of the first blocks during execution of the first operation, the sequencer of the semiconductor memory device suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
It would have been obvious to one having ordinary skill in the art to recognize that the first command set, the second command set and the third command set are sent by the memory controller.
Regarding claim 2, claim 2 of the patent recites the memory system of claim 1, wherein:
the second operation does not cause a change of a threshold voltage of the second memory cell of the one of the second blocks, and
the third operation does not cause a change of a threshold voltage of the first memory cell of the another one of the first blocks.
Regarding claim 3, claim 3 of the patent recites the memory system of claim 1, wherein:
in each of the first blocks, a plurality of the first memory cells are connected in series to form a first NAND string,
in each of the second blocks, a plurality of the second memory cells are connected in series to form a second NAND string,
the first operation causes a change of the threshold voltages of the first memory cells belonging to the first NAND string of the one of the first blocks,
the second operation accesses one of the second memory cells belonging to the second NAND string of the one of the second blocks, and
the third operation accesses one of the first memory cells belonging to the first NAND string of the another one of the first blocks.
Regarding claim 4, claim 4 of the patent recites the memory system of claim 3, wherein:
the first operation is an erase operation, and
each of the second operation and the third operation is a read operation.
Regarding claim 5, claim 5 of the patent recites the memory system of claim 4, wherein a timing at which the sequencer executes the second operation in response to the second command set during the execution of the first operation changes based on a timing at which the second command set is received.
Regarding claim 6, claim 6 of the patent recites the memory system of claim 4, wherein the first operation is resumed regardless of an instruction from the external memory controller after data read by the second operation has been output.
Regarding claim 7, claim 7 of the patent recites the memory system of claim 4, wherein the first operation is resumed based on an external command that has been received after data read by the second operation has been output.
Regarding claim 8, claim 8 of the patent recites the memory system of claim 3, wherein the semiconductor memory device further includes:
a first bit line connected to first ends of the first NAND strings of the first blocks; and
a second bit line connected to first ends of the second NAND strings of the second blocks.
Regarding claim 9, claim 9 of the patent recites the memory system of claim 8, wherein the semiconductor memory device further includes:
a first source line connected to second ends of the first NAND strings of the first blocks; and
a second source line connected to second ends of the second NAND strings of the second blocks.
Regarding claim 10, claim 10 of the patent recites the memory system of claim 1, wherein:
the semiconductor memory device further includes:
a third plane including a plurality of third blocks, each of the third blocks including a third memory cell; and
a fourth plane including a plurality of fourth blocks, each of the fourth blocks including a fourth memory cell,
the first driver is configured to supply power to the first plane and the third plane, and
the second driver is configured to supply power to the second plane and the fourth plane.
Regarding claim 11, claim 11 of the patent recites the memory system of claim 10, wherein:
in each of the first blocks, a plurality of the first memory cells are connected in series to form a first NAND string,
in each of the second blocks, a plurality of the second memory cells are connected in series to form a second NAND string,
in each of the third blocks, a plurality of the third memory cells are connected in series to form a third NAND string, and
in each of the fourth blocks, a plurality of the fourth memory cells are connected in series to form a fourth NAND string.
Regarding claim 12, claim 12 of the patent recites the memory system of claim 11, wherein the semiconductor memory device further includes:
a first bit line connected to first ends of the first NAND strings of the first blocks;
a second bit line connected to first ends of the second NAND strings of the second blocks;
a third bit line connected to first ends of the third NAND strings of the third blocks;
a fourth bit line connected to first ends of the fourth NAND strings of the fourth blocks;
a first source line connected to second ends of the first NAND strings of the first blocks;
a second source line connected to second ends of the second NAND strings of the second blocks;
a third source line connected to second ends of the third NAND strings of the third blocks; and
a fourth source line connected to the second ends of the fourth NAND strings of the fourth blocks.
Regarding claim 13, claim 13 of the patent recites the memory system of claim 12, wherein:
during the first operation, the first driver of the semiconductor memory device applies an erase voltage to the first source line, and
when the memory controller sends the second command set during the execution of the first operation, the sequencer of the semiconductor memory device executes the second operation in parallel with the first operation without discharging the first source line.
Regarding claim 14, claim 14 of the patent recites the memory system of claim 13, wherein when the memory controller sends the third command set during the execution of the first operation, the sequencer of the semiconductor memory device suspends the first operation while discharging the first source line, executes the third operation, and resumes the first operation upon completion of the third operation.
Regarding claim 15, claim 15 of the patent recites the memory system of claim 14, wherein:
during the first operation, the first driver of the semiconductor memory device applies an erase voltage to the first source line, and
when the memory controller sends a fourth command set that instructs execution of a fourth operation to one of the third memory cells of the third NAND string of one of the third blocks during execution of the first operation, the sequencer of the semiconductor memory device suspends the first operation without discharging the first source line, executes the fourth operation, and resumes the first operation upon completion of the third operation.
It would have been obvious to one having ordinary skill in the art to recognize that the second, the third and the fourth command sets in claims 13-15 are sent by the controller.
Regarding claims 16-19, claim 1 of the patent recites a memory system comprising a
a semiconductor memory device; and
a memory controller (claim 1, line 11) configured to send a command set to the semiconductor memory device,
wherein the semiconductor memory device includes:
a first plane including one or more first blocks of memory cells powered by a first driver (claim 1, lines 2-3 and lines 7-8);
a second plane including one or more second blocks of memory cells powered by a second driver (claim 1, lines 4-6 and lines 7-8); and
a sequencer (claim 1, line 12).
It would have been obvious to one having ordinary skill in the art to recognize that the memory system of claim 16 of the instant application and the memory system of claim 1 of the patent are identical in structure; therefore, the differences between claims 16-19 and claim 1 of the patent are only functional limitations.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 11,783,899. Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one having ordinary skill in the art to recognize that the memory system of claims 1-19 of the instant application and the memory system of claims 1-14 of the patent are identical in structure; therefore, the differences of two sets of claims are only functional limitations and that the memory device is a NAND-type nonvolatile memory.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,532,363. Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one having ordinary skill in the art to recognize that the memory system of claims 1-19 of the instant application and the memory system of claims 1-19 of the patent are identical in structure; therefore, the differences of two sets of claims are only functional limitations and that the memory device is a NAND-type nonvolatile memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Imamoto (US 2020/020934) discloses a semiconductor memory device including a plurality of planes, a comparator and a controller to execute read and write operations.
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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