DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed before March 16, 2013, is being examined under the pre-AIA status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 4-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,191,863. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-17 of U.S. Patent No. 12,191,863 anticipates the claims 1 and 4-19.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 20 recites “receiving the first adjustment of the duty cycle of the signal simultaneous with the second adjustment”, which renders the claim indefinite. The original disclosure only discloses sequential adjustment of coarse adjustment and the fine adjustment. See figs. 3-4.
Further clarification is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12 and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 10 recites the limitation “the fine adjustment value and the coarse adjustment value”. There is insufficient antecedent basis for this limitation in the claim. In addition, it’s unclear what the relationships are between the second adjustment amount and the first adjustment amount, and the fine adjustment value and the coarse adjustment value, respectively.
In addition, claim 10 recites a phrase “a first plurality of serially-coupled adjustor cells each configured to apply at least a portion of the second adjustment amount and at least a portion of the second adjustment amount to the signal”. Which renders the claim indefinite. The phrase repeats at least a portion of the second adjustment amount tow times. It’s unclear whether “apply at least a portion of the second adjustment amount and at least a portion of the second adjustment amount” refers to apply at least a portion of the first adjustment amount and at least a portion of the second adjustment amount, apply at least a portion of the second adjustment amount, apply at least a portion of the first adjustment amount, or something else.
Claims 11-12 are rejected based on the dependency from claim 10.
Claim 18 recites “wherein the second range of values is equal to the first value”, which renders the claim indefinite. It’s unclear why a range of values is equal to a value.
Claim 19 recites “the second range of values is equal to 1.2 of the first value”, which renders the claim indefinite. It’s unclear why a range of values is equal to a value, e.g. 1.2 of the first value. It’s unclear what 1.2 of the first value is.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
(e) the invention was described in a patent granted on an application for patent by another filed in the United States before the invention thereof by the applicant for patent, or on an international application by another who has fulfilled the requirements of paragraphs (1), (2), and (4) of section 371(c) of this title before the invention thereof by the applicant for patent.
Claim(s) 1-5, 7, 13-16 and 18-20 is/are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Kizer et al. (US 2004/0075462).
Regarding claim 1, Kizer discloses a dynamic random access memory (DRAM) device [e.g. fig. 1, para. 0038] comprising: a duty cycle adjustment circuit [e.g. 10 fig. 1A/11 fig. 1B], when enabled by a control signal [e.g. a signal to provide clock signal, see 302 fig. 14] provided by a memory controller [see at least para. 0038], configured to: receive a signal [e.g. 20], receive a first adjustment value to adjust a duty cycle of the signal by a first adjustment amount, and receive a second adjustment value to adjust the duty cycle of the signal by a second adjustment amount, wherein the second adjustment amount is less than the first adjustment amount [e.g. fine and coarse adjustments; or two adjustments have different adjusted mounts].
Regarding claim 2, Kizer discloses the DRAM device of claim 1, further comprising a clock distribution tree [see at least para. 0039, clock 18 is provided to an electronic system; or it’s notorious well-known to provide a clock distribution tree to be used in a system for synchronization, the official notice of the forgoing fact is taken] coupled to the duty cycle adjustment circuit.
Regarding claim 3, Kizer discloses the DRAM device of claim 2, wherein duty cycle adjustment circuit is located before the clock distribution tree [see at least fig. 1].
Regarding claim 4, Kizer discloses the DRAM device of claim 1, wherein the duty cycle adjustment circuit is configured to adjust the rise time of the signal, the fall time of the signal, or both [see at least figs. 4A-4C, 5A-5E].
Regarding claim 5, Kizer discloses the DRAM device of claim 1, wherein the signal comprises a clock signal.
Regarding claim 7, Kizer discloses the DRAM device of claim 5, further comprising a duty cycle detection circuit [e.g. 24/27 fig. 1] configured to monitor the duty cycle of the signal.
Regarding claim 13, Kizer discloses a method, comprising: receiving an enable signal from a memory controller at a duty cycle adjustment circuit of a dynamic random access memory (DRAM); enabling the duty cycle adjustment circuit of the DRAM responsive to the enable signal; receiving a signal at a duty cycle adjustor of the duty cycle adjustment circuit; applying a first adjustment to the duty cycle of the signal based on a respective first adjustment value; and applying a second adjustment of the duty cycle of the signal based on a respective second adjustment value, wherein the second adjustment value is less than the first adjustment value. This claim is merely methods to operate the circuit having structure recited in claim 1. Since Kizer et al. teaches the structure, the methods to operate such a circuit are similarly disclosed. Please see rejection of claim 1.
Regarding claim 14, Kizer discloses the method of claim 13, further comprising during a duty cycle adjustment operation: receiving the first adjustment value to apply to the signal to perform the first adjustment of the duty cycle of the clock signal; and receiving the second adjustment value to apply to the signal to perform the second adjustment of the duty cycle of the clock signal.
Regarding claim 15, Kizer discloses the method of claim 14, wherein the receiving of the second adjustment value is performed after completion of reception of the first adjustment value [since the claim does not specify fine adjustment and coarse adjustment, it could be two adjustments having second adjustment value is performed after completion of reception of the first adjustment value].
Regarding claim 16, Kizer discloses the method of claim 13, wherein the signal comprises an internal clock signal [e.g. 20].
Regarding claim 18 (as best understood), Kizer discloses the method of claim 13, wherein the first adjustment value is a first value selected from a first range of values, and the second adjustment value is a second value selected from a second range of values, wherein the second range of values is equal to the first value [e.g. the first value is equal to the second value].
Regarding claim 19 (as best understood), Kizer discloses the method of claim 18, wherein the second range of values is equal to 1.2 of the first value [e.g. the second value is equal to the first value times 1.2].
Regarding claim 20, Kizer discloses the method of claim 13, further comprising receiving the first adjustment of the duty cycle of the signal simultaneous with the second adjustment [see at least para. 0052, in the case where both the coarse and the fine duty cycle adjustment signals are in digital form, they may be combined to provide an input to a single DAC with current sources having different values, such that the least significant bit or bits are provided by the fine duty cycle adjustment signal and the most significant bit or bits are provided by the coarse duty cycle adjustment signal; also, see fig. 1].
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kizer et al. (US 2004/0075462) in view of Blum (US 5,757,218).
Regarding claim 6, Kizer discloses the DRAM device of claim 5. Kizer does not disclose an output buffer. However, it’s known to utilize an output buffer to provide an output signal to a duty cycle corrector. For example, Blum discloses an output buffer [see at least 116 fig. 1, Col. 3, lines 38-50] to provide an output signal to a duty cycle corrector [e.g. 104, 106], such that he combination discloses further comprising an output buffer configured to receive the clock signal from the duty cycle adjustment circuit and output data [e.g. corrected clock, clock to tree, etc] based, at least in part, on the clock signal. Therefore, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify the device disclosed by Kizer in accordance with the teaching of Blum regarding an intervening element to buffer a clock signal/to facilitate compensation [see at least 116 fig. 1, Col. 3, lines 38-50].
Claims 8-9 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kizer et al. (US 2004/0075462) in view of Lin (US 6,940,328).
Regarding claim 8, Kizer discloses the DRAM device of claim 1, except further comprising a signal generator coupled to the duty cycle adjustment circuit and configured to receive an external signal, the signal generator further configured to provide the signal based on the external signal to the duty cycle adjustment circuit.
However, it is known to use a buffer to receive a signal and to delay the signal to provide an output signal. For example, Lin discloses further comprising: a signal generator [310 fig. 3] coupled to the duty cycle adjustment circuit and configured to receive an external signal [CLK fig. 3], the signal generator further configured to delay the external signal to provide the signal to the duty cycle adjustment circuit. Therefore, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify the device disclosed by Kizer in accordance with the teaching of Lin regarding a buffer for the purpose of utilizing a well-known buffer to help control the external signal.
Regarding claim 9, the combination discussed above discloses the DRAM device of claim 8, wherein the signal generator delays the external signal to provide the signal.
Claims 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kizer et al. (US 2004/0075462) in view of Wu et al. (US 2013/0229216).
Regarding claim 10 (as best understood), Kizer discloses the DRAM device of claim 1, except wherein the duty cycle adjustment circuit comprises a first plurality of serially-coupled adjustor cells each configured to apply at least a portion of the second adjustment amount and at least a portion of the second adjustment amount to the signal based on the fine adjustment value and the coarse adjustment value, respectively. However, Wu discloses a duty cycle adjustment circuit [e.g. 16, 18 fig. 1] comprises a first plurality of serially-coupled adjustor cells [e.g. 164 and 166, 170, 172 fig. 5A; 346, 348/334 and the cell having 336, 342 fig. 10A/10C] each configured to apply at least a portion of the second adjustment amount and at least a portion of the second adjustment amount to the signal based on the fine adjustment value and the coarse adjustment value, respectively. Therefore, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify the device disclosed by Kizer in accordance with the teaching of Wu regarding elements of the coarse turning circuit and the fine tuning circuit in order to improve accuracy/to provide inflexible in different applications [para. 0004].
Regarding claim 11 (as best understood), the combination discussed above discloses the DRAM device of claim 10, wherein the duty cycle adjustment circuit further comprises a second plurality of serially-coupled adjustor cells [e.g. 52s fig. 3A] each configured to selectively apply only a portion of the first adjustment amount to the signal based on the first adjustment value.
Regarding claim 12 (as best understood), the combination discussed above discloses the DRAM device of claim 10, wherein the plurality of adjuster cells each comprise an inverter.
Claim 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kizer et al. (US 2004/0075462) in view of Miyano (US 2011/0227618).
Regarding claim 17, Kizer discloses the method of claim 16, except further comprising receiving an external clock signal at the DRAM. However, it’s well known to receive an external clock signal at a DRAM. For example, Miyano discloses to receive an external clock signal at a DRAM [paras. 0003-0004]. Therefore, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify the device disclosed by Kizer in accordance with the teaching of Miyano regarding an external clock signal in order to use an external as a timing signal [paras. 0003-0004].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 9:00-5:30.
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/PATRICK C CHEN/Primary Examiner, Art Unit 2842