DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Arimoto et al. (US Pub. 2006/0013030) in view of Kang et al. (US Pat. 9,627,026).
Regarding claim 1, 11, 17, and 19, Fig. 79 of Arimoto discloses a memory device comprising:
a memory cell array [MSA, Fig. 1] including a plurality of memory cells [MC, Fig. 1];
a row decoder [RCDB, Fig. 88] connected with the memory cell array through a plurality of word lines [WL], wherein the row decoder is configured to select a word line corresponding to an address signal [43, Fig. 32] and to control the selected word line;
a column decoder [RCDB, Fig. 88] connected with the memory cell array through a plurality of bit lines [as shows in Fig. 79], wherein the column decoder is configured to select a bit line corresponding to the address signal [column address];
a sense amplifier [SA, Fig. 79] configured to sense a voltage of the selected bit line [BLL, Fig. 79] and to control the voltage of the selected bit line;
an input and output circuit configured to transmit and receive data with the sense amplifier [since data are input and output to and from sense amplifier, and input/output circuit is inherent]; and
a refresh control circuit [10, Fig. 11] configured to control a refresh operation performed by the sense amplifier,
wherein the sense amplifier includes a plurality of bit line sense amplifiers [SA, Fig. 79] connected with the memory cell array through the plurality of bit lines [BLL, ZBLL],
wherein each of the plurality of bit line sense amplifiers includes:
an equalization circuit [BEQL] connected with a bit line and [BLL] a complementary bit line [ZBLL];
a data sensing circuit [SA] connected with at least one of the bit line [BLL] or the complementary bit line [ZBLL], wherein the data sensing circuit is configured to sense data in the memory cell and to output a data sense signal; and
Arimoto discloses all claimed invention, but does not specifically disclose a sense amplification circuit connected with the bit line and the complementary bit line, wherein the sense amplification circuit is configured to perform the refresh operation on the memory cell, and wherein the refresh control circuit is configured to receive the data sense signal and, based on the data of the memory cell being “0,” output a first control signal that enables the sense amplification circuit to skip the refresh operation. However, Fig. 6 of Kang discloses a sense amplification circuit [combination of 300_1, 500_1] connected with the bit line and the complementary bit line, wherein the sense amplification circuit is configured to perform the refresh operation on the memory cell, and wherein the refresh control circuit is configured to receive the data sense signal and, based on the data of the memory cell being “0,” output a first control signal that enables the sense amplification circuit to skip the refresh operation [as discloses in col. 4, lines 22 to 30, when data is “0”, refresh operation is skipped].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kang’s memory device with refreshing operation to teachings of Arimoto’s memory device having sense amplfier such that Arimoto memory device operates to skip refreshing operation in according to Kang’s teachings for the purpose of reducing refreshing current and extend data retention time [col. 4, line 39 to 44].
Regarding claims 2, 18, and 20, Arimoto discloses all claimed invention, but does not specifically disclose wherein the refresh control circuit is configured to, based on the data of the memory cell being “1,” output a second control signal that enables the sense amplification circuit to perform the refresh operation. However, col. 4 lines 22 to 26 of Kang discloses wherein the refresh control circuit is configured to, based on the data of the memory cell being “1,” output a second control signal that enables the sense amplification circuit to perform the refresh operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kang’s memory device with refreshing operation to teachings of Arimoto’s memory device having sense amplfier such that Arimoto memory device operates to skip refreshing operation in according to Kang’s teachings for the purpose of reducing refreshing current and extend data retention time [col. 4, line 39 to 44].
Regarding claim 3, Fig. 79 of Arimoto discloses wherein the first control signal is configured to deactivate a word line [SWL] associated with the memory cell and activate an equalization control signal [BLEQL].
Regarding claim 4, Fig. 79 of Arimoto discloses wherein the equalization circuit [BEQL] is configured to charge the bit line and the complementary bit line [ZBLL] to a precharge voltage [VBL] based on the equalization control signal being activated.
Regarding claim 5, Fig. 79 of Arimoto discloses wherein the word line is deactivated after the sense amplification circuit performs an amplification operation for a time period shorter than a predetermined first threshold time period, the amplification operation amplifying a voltage difference between the bit line and the complementary bit line based on a first power voltage and a second power voltage [as shows in Fig. 81].
Regarding claim 6, Fig. 79 of Arimoto discloses wherein the sense amplification circuit [SA] is configured to, based on the second control signal, perform an amplification operation for a time period longer than a predetermined second threshold time period, the amplification operation amplifying a voltage difference between the bit line and the complementary bit line based on a first power voltage and a second power voltage [as shows in Fig. 81].
Regarding claim 7, Fig. 79 of Arimoto discloses wherein the data sensing circuit is configured to sense the data in the memory cell after a capacitor [MQ] of the memory cell is connected with the bit line.
Regarding claim 8, Fig. 79 of Arimoto discloses wherein the data sensing circuit [SA] is configured to sense the data in the memory cell based on a voltage of at least one of the bit line [BLL] or the complementary bit line [ZBLL] falling within a predetermined range.
Regarding claim 9, Fig. 79 of Arimoto discloses wherein, before the capacitor [MQ] of the memory cell is connected with the bit line, the bit line and the complementary bit line are charged to a precharge voltage [VBL] by the equalization circuit.
Regarding claim 10, Fig. 79 of Arimoto discloses wherein the data sensing circuit and the refresh control circuit are configured to receive an operation signal, and wherein the data sensing circuit and the refresh control circuit are configured to be activated based on the operation signal [ZSOP, SON] being in a first logic state, and wherein the data sensing circuit and the refresh control circuit are configured to be deactivated based on the operation signal being in a second logic state.
Regarding claim 12, Fig. 79 of Arimoto discloses wherein the data sensing circuit is connected with the complementary bit line [ZBLL] and is configured to output complementary bit line data in an active state, the complementary bit line data being inverted data of the data of the memory cell.
Regarding claim 14, Fig. 79 of Arimoto discloses wherein the data sensing circuit [SA] is connected with the bit line and is configured to output bit line data in an active state, the bit line data being the data of the memory cell [MC].
Regarding claim 16, Fig. 79 of Arimoto discloses wherein the memory device is a dynamic random access memory.
Allowable Subject Matter
Claim 13, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior art does not teach or suggest either alone or in combination wherein the refresh control circuit includes: a NAND circuit configured to receive the operation signal and the complementary bit line data and to perform a NAND operation; and an inverter configured to invert an output signal of the NAND circuit and to generate an inverted data signal, wherein the inverted data signal generated by the inverter is an output of the refresh control circuit.
Regarding claim 15, the prior art does not teach or suggest either alone or in combination wherein the refresh control circuit includes: a first inverter configured to invert the bit line data and to generate a first inverted data signal; a NAND circuit configured to receive the operation signal and the first inverted data signal and to perform a NAND operation; and a second inverter configured to invert the output signal of the NAND circuit and to generate a second inverted data signal, wherein the second inverted data signal generated by the second inverter is an output of the refresh control circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
Prosecution Insights