DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
This Office Action is responsive to the application filed 03 December 2024 and the preliminary amendment filed 07 February 2025.
Claims 2-21 are pending and have been presented for examination.
Claim 1 has been cancelled.
Claim Objections
Claim 9 is objected to because of the following informalities: the limitation “the second information comprises a deserializer” in line 3 does not make sense in view of the claim as a whole. This appears to be a typo and will be interpreted by the Examiner as “the second interface comprises a deserializer”.
Claim 10 is objected to because of the following informalities: the claim recites “the second conductive communication link” in line 4. This is not consistent with claim 2 which recites “a second communication link”. The Examiner recommends amending either claim 2 or claim 10 to use consistent terms.
Claim 19 is objected to because of the following informalities: the limitation “the second information comprises a deserializer” in line 2 does not make sense in view of the claim as a whole. This appears to be a typo and will be interpreted by the Examiner as “the second interface comprises a deserializer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 13-14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the information" in line 7. There is insufficient antecedent basis for this limitation in the claim. Claim 2 set forth “first information” and “second information”, therefore it is not clear which of the “first information” and “second information” is being referenced.
Claim 4 is also rejected based on its dependency to claim 3.
Claim 13 recites the limitation "the information" in line 4. There is insufficient antecedent basis for this limitation in the claim. Claim 12 set forth “first information” and “second information”, therefore it is not clear which of the “first information” and “second information” is being referenced.
Claim 14 is also rejected based on its dependency to claim 13.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 5-7, 12 and 15-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 9 and 10 of U.S. Patent No. 11,276,440. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of the ‘440 patent.
With respect to claims 2 and 21: the claims of the instant application are directed to a memory controller while the claims of the ‘440 patent are directed to an integrated circuit. The functionally of the integrated circuit of the ‘440 patent is the same as the functionality of the instant application as shown below. The use of a memory controller to manage and control a memory is well known in the art. A memory controller is used to provide a communication interface to a memory device. One of ordinary skill in the art would have been motivated to build a controller, as described by the instant application, to provide the signals that the integrated circuit of the ‘440 patent is designed to accept. This will allow the integrated circuit to actually be used in the manner claimed in the ‘440 patent.
With respect to claim 12: the instant application is directed to a method of operating a memory controller while the ‘440 patent is directed to an integrated circuit. The use of a memory controller to manage and control a memory is well known in the art. A memory controller is used to provide a communication interface to a memory device. One of ordinary skill in the art would have been motivated to build a controller, as described by the instant application, to provide the signals that the integrated circuit of the ‘440 patent is designed to accept. This will allow the integrated circuit to actually be used in the manner claimed in the ‘440 patent.
11,276,440
18/967,513
1. An integrated circuit comprising:
(A) a first command/address (CA) interface to receive a first memory access command from a first CA link, the first memory access command specifying a first memory access to a memory location in a first dynamic random access memory (DRAM) array,
(E) wherein the first CA interface is operable to receive a first test pattern in a CA interface calibration mode;
(A) a first data interface to transmit first data in association with the first memory access command;
(B) a second command/address (CA) interface to receive a second memory access command from a second CA link, the second memory access command specifying a second memory access to a second memory location in a second dynamic random access memory (DRAM) array, wherein the second CA interface is operable to receive a second test pattern in a CA interface calibration mode;
(B) a second data interface to transmit second data in association with the second memory access command;
(E F)and loop-back circuitry operable to output the bits of the first test pattern on a first data link, via the first data interface, and to output the bits of the second test pattern on a second data link, via the second data interface.
2. The integrated circuit of claim 1,
(G) wherein the first data interface and the second data interface are each bidirectional interfaces, the first data interface is to transfer data for the first DRAM array in a normal mode of operation, and the second bidirectional data interface is to transfer data for the second DRAM array in the normal mode of operation.
2. (New) A memory controller to control a dynamic random access memory (DRAM) device, the memory controller comprising:
(A) a first interface to transfer first information with the DRAM device over a first conductive communication link;
(B) and a second interface to transfer second information with the DRAM device over a second communication link;
(C) wherein: the memory controller has a first operational mode and a second operational mode;
(D) in the first operational mode, the memory controller is operable to transfer the first information and the second information with the DRAM device, respectively using the first interface and the second interface;
(E) and in the second operational mode, the memory controller is operable to transmit a test pattern to the DRAM device, via the first interface, and is operable to receive feedback from the DRAM device via the second interface,
(F) wherein the feedback is derived from the test pattern received by the DRAM device and looped back to the memory controller.
7. (New) The memory controller of claim 2
(G) wherein at least one of the first interface or the second interface is operable to, in the first operational mode, transmit at least one of bits of a memory command or bits of a DRAM memory address to the DRAM device.
Claim 8
Claims 5&6
9. A method of operation in an integrated circuit, the method comprising:
(A B) receiving a first memory access command via a first command/address (CA) interface from a first CA link, the first memory access command specifying a first memory access to a memory location in a first dynamic random access memory (DRAM) array; transmitting first data in association with the first memory access command via a first data interface; receiving a second memory access command via a second command/address (CA) interface from a second CA link, the second memory access command specifying a second memory access to a memory location in a second DRAM array; transmitting second data in association with the second memory access command via a second data interface;
(C) during a CA interface calibration mode, receiving a first test pattern via the first CA interface and using loop-back circuitry operable in the CA interface calibration mode to output the bits of the first test pattern on a first data link, via the first data interface; and during the CA interface calibration mode, receiving a second test pattern via the second CA interface and using loop-back circuitry operable in the CA interface calibration mode to output the bits of the second test pattern on a second data link, via the second data interface.
12. (New) A method of operation in a memory controller,
(A) wherein the memory controller comprises a first interface and a second interface and wherein the memory controller is operable to control a dynamic random access memory (DRAM) device, the method comprising:
(B) in a first operational mode, transferring first information with the DRAM device, using the first interface, via a first conductive communication link, and transferring second information with the DRAM device, using the second interface, via a second conductive communication link;
(C) and in a second operational mode, transmitting a test pattern to the DRAM device, via the first interface, receiving feedback from the DRAM device, via the second interface, wherein the feedback is derived from the test pattern received by the DRAM device and looped back to the memory controller.
17. (New) The method of claim 12
(A B C) wherein at least one of the first information or the second information which is transmitted in the first operational mode comprises bits of at least one of: (1) a memory command or (2) a DRAM memory address.
Claim 10
Claims 15&16
1. An integrated circuit comprising:
(A B) a first command/address (CA) interface to receive a first memory access command from a first CA link, the first memory access command specifying a first memory access to a memory location in a first dynamic random access memory (DRAM) array, wherein the first CA interface is operable to receive a first test pattern in a CA interface calibration mode; a first data interface to transmit first data in association with the first memory access command; a second command/address (CA) interface to receive a second memory access command from a second CA link, the second memory access command specifying a second memory access to a second memory location in a second dynamic random access memory (DRAM) array,
(C) wherein the second CA interface is operable to receive a second test pattern in a CA interface calibration mode; a second data interface to transmit second data in association with the second memory access command; and loop-back circuitry operable to output the bits of the first test pattern on a first data link, via the first data interface, and to output the bits of the second test pattern on a second data link, via the second data interface.
21. (New) A memory controller to control a dynamic random access memory (DRAM) device, the memory controller comprising:
(A) a command/address interface to transfer command/address information with the DRAM device;
(B) and a data interface to transfer data with the DRAM device;
(C) wherein the memory controller is operable, in a calibration mode, to transmit a test pattern to the DRAM device, via the command/address interface, and is operable to receive feedback from the DRAM device via the data interface, wherein the feedback is derived from the test pattern received by the DRAM device and looped back to the memory controller.
Claims 2, 5, 12, 18 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 8 of U.S. Patent No. 11,727,966. Although the claims at issue are not identical, they are not patentably distinct from each other.
With respect to claims 2 and 21: the claims of the instant application are directed to a memory controller while the claims of the ‘966 patent are directed to a DRAM. The functionally of the DRAM of the ‘966 patent is the same as the functionality of the instant application as shown below. The use of a memory controller to manage and control a memory is well known in the art. A memory controller is used to provide a communication interface to a memory device. One of ordinary skill in the art would have been motivated to build a controller, as described by the instant application, to provide the signals that the DRAM of the ‘966 patent is designed to accept. This will allow the DRAM to actually be used in the manner claimed in the ‘966 patent.
With respect to claim 12: the instant application is directed to a method of operating a memory controller while the ‘966 patent is directed to a DRAM. The use of a memory controller to manage and control a memory is well known in the art. A memory controller is used to provide a communication interface to a memory device. One of ordinary skill in the art would have been motivated to implement a method for a memory controller, as described by the instant application, to provide the signals that the DRAM of the ‘966 patent is designed to accept. This will allow the DRAM to actually be used in the manner claimed in the ‘966 patent.
11,727,966
18/967,513
1. A dynamic random access memory (DRAM) device comprising:
(A) a memory array; a command/address (CA) interface that is operable, in a normal operating mode, to receive commands from a CA link that specify accesses to memory locations in the memory array,
(E) and wherein the CA interface is operable, in a CA interface calibration mode, to receive a test pattern from the CA link;
(D) a data interface to transfer data in connection with the commands that specify accesses to memory locations in the memory array;
(F) and loop-back circuitry to provide a feedback path from the CA interface to the data interface during the CA interface calibration mode.
2. The DRAM device of claim 1 wherein: the memory array is a first memory array,
(A) the CA interface is a first CA interface, the data interface is a first data interface, and the CA link is a first CA link; the DRAM device further comprises a second memory array,
(B) a second CA interface, a second data interface and a second CA link; the second CA interface is operable to receive commands from the second CA link that specify accesses to memory locations in the second memory array;
(E) the second CA interface is operable to receive a test pattern from the second CA link;
(F) and the loop-back circuitry is operable to provide a feedback path from the second CA interface to the second data interface during the CA interface calibration mode.
2. (New) A memory controller to control a dynamic random access memory (DRAM) device, the memory controller comprising:
(A) a first interface to transfer first information with the DRAM device over a first conductive communication link;
(B) and a second interface to transfer second information with the DRAM device over a second communication link;
wherein: the memory controller has a first operational mode and a second operational mode;
(D) in the first operational mode, the memory controller is operable to transfer the first information and the second information with the DRAM device, respectively using the first interface and the second interface;
(E) and in the second operational mode, the memory controller is operable to transmit a test pattern to the DRAM device, via the first interface, and is operable to receive feedback from the DRAM device via the second interface,
(F) wherein the feedback is derived from the test pattern received by the DRAM device and looped back to the memory controller.
Claim 8
Claim 5
1. A dynamic random access memory (DRAM) device comprising:
(A) a memory array; a command/address (CA) interface that is operable, in a normal operating mode, to receive commands from a CA link that specify accesses to memory locations in the memory array,
(C) and wherein the CA interface is operable, in a CA interface calibration mode, to receive a test pattern from the CA link; a data interface to transfer data in connection with the commands that specify accesses to memory locations in the memory array;
(D) and loop-back circuitry to provide a feedback path from the CA interface to the data interface during the CA interface calibration mode.
2. The DRAM device of claim 1 wherein:
(A B) the memory array is a first memory array, the CA interface is a first CA interface, the data interface is a first data interface, and the CA link is a first CA link; the DRAM device further comprises a second memory array, a second CA interface, a second data interface and a second CA link; the second CA interface is operable to receive commands from the second CA link that specify accesses to memory locations in the second memory array; the second CA interface is operable to receive a test pattern from the second CA link; and the loop-back circuitry is operable to provide a feedback path from the second CA interface to the second data interface during the CA interface calibration mode.
12. (New) A method of operation in a memory controller,
(A) wherein the memory controller comprises a first interface and a second interface and wherein the memory controller is operable to control a dynamic random access memory (DRAM) device, the method comprising:
(B) in a first operational mode, transferring first information with the DRAM device, using the first interface, via a first conductive communication link, and transferring second information with the DRAM device, using the second interface, via a second conductive communication link;
(C) and in a second operational mode, transmitting a test pattern to the DRAM device, via the first interface,
(D) receiving feedback from the DRAM device, via the second interface, wherein the feedback is derived from the test pattern received by the DRAM device and looped back to the memory controller.
Claim 8
Claim 18
1. A dynamic random access memory (DRAM) device comprising:
(A) a memory array; a command/address (CA) interface that is operable, in a normal operating mode, to receive commands from a CA link that specify accesses to memory locations in the memory array,
(B) and wherein the CA interface is operable, in a CA interface calibration mode, to receive a test pattern from the CA link;
(A) a data interface to transfer data in connection with the commands that specify accesses to memory locations in the memory array;
(C) and loop-back circuitry to provide a feedback path from the CA interface to the data interface during the CA interface calibration mode.
2. The DRAM device of claim 1 wherein: (A B) the memory array is a first memory array, the CA interface is a first CA interface, the data interface is a first data interface, and the CA link is a first CA link; the DRAM device further comprises a second memory array, a second CA interface, a second data interface and a second CA link; the second CA interface is operable to receive commands from the second CA link that specify accesses to memory locations in the second memory array; the second CA interface is operable to receive a test pattern from the second CA link; and the loop-back circuitry is operable to provide a feedback path from the second CA interface to the second data interface during the CA interface calibration mode.
21. (New) A memory controller to control a dynamic random access memory (DRAM) device, the memory controller comprising:
(A) a command/address interface to transfer command/address information with the DRAM device; and a data interface to transfer data with the DRAM device;
(B) wherein the memory controller is operable, in a calibration mode, to transmit a test pattern to the DRAM device, via the command/address interface,
(C) and is operable to receive feedback from the DRAM device via the data interface, wherein the feedback is derived from the test pattern received by the DRAM device and looped back to the memory controller.
Allowable Subject Matter
Claims 8-11 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3, 4, 13 and 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the limitations of claims 8-11 and 19-20 are not anticipated, or rendered obvious, in view of the claims of the parent application. Claims 1, 12 and 21 are commensurate in scope with the claims of U.S. Patents 11,727,966 and 11,276,440 and are considered patentably distinct over the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2136