DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 12/04/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 12/04/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "the logic elements" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 12-13, 15-16 & 20 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Grover et al (US20200388330)
Regrading claim 1, Grover discloses a memory circuit comprising: a memory element configured to store a bit of data and to provide the bit of data when data are read from a computing cell(FIG 4; memory element 130 having bias elements arranged to perform particular computing operation within memory array 132(storing bit data)) ; and a logic element coupled to of the memory element and configured to receive a select signal (FIG 4-5; [0060] discloses a logic element 140 coupled to 130 and receives select signal 150).
Regrading claim 2, Grover discloses wherein the logic element is configured to output a high level or a low level based on the select signal and a signal from a data output terminal of the memory element (FIG 4-5; [0066] discloses 140 receiving signal 150 and a signal 132 and outputs data 160A).
Regrading claim 3, Grover discloses wherein the computing cell is configured to drive a voltage of a bit line (FIG 4-5; BLs).
Regrading claim 4, Grover discloses further comprising a voltage detector coupled to a bit line (FIG 4-5; 148 coupled to BLs).
Regrading claim 5, Grover discloses wherein the memory circuit is configured to determine a number of computing cells having a particular value based on a voltage of a bit line (FIG 4-5; [0072] discloses determining values individual bit values logic ones or zero, and any number of bias bitcells being grouped to select a suitable bias value of computing cells).
Regrading claim 6, Grover discloses wherein the memory circuit is configured to determine a number of computing cells having a particular value based on at least one of a total number of computing cells, a capacitance of a capacitor, a load capacitance, and a voltage of a bit line(FIG 4-5; [0072] discloses determining values individual bit values logic ones or zero, and any number of bias bitcells being grouped to select a suitable bias value of computing cells and a voltage of a bit line e.g., on BL).
Regrading claim 7, Grover discloses wherein the computing cell is configured to drive a voltage of a bit line higher when the memory element contains a 1 data value and when the select signal is high (FIG 4-5; [0068 & 0073] discloses applying bias voltage e.g., high voltage when value is 1).
Regrading claim 8, Grover discloses wherein the logic element of the computing cell comprises a NOR gate and the NOR gate receives an inversed signal from the memory element and an inversed select signal (FIG 4-5; [0060] discloses computing operations including gating operation e.g., NOR gate and gate receiving inversed signal due to the NOR gating from 132 and 150).
Regrading claim 9, Grover discloses wherein the logic element of the computing cell comprises an AND gate and the AND gate receives a signal from the data output terminal of the memory element and the select signal (FIG 4-5; [0060] discloses computing operations including gating operation e.g., AND gate and gate receiving inversed signal due to the AND gating from 132 and 150).
Regrading claim 12, Grover discloses wherein the logic element of the computing cell comprises an OR gate and the OR gate receives an inversed signal from the memory element and an inversed select signal (FIG 4-5; [0060] discloses computing operations including gating operation e.g., OR gate and gate receiving inversed signal due to the OR gating from 132 and 150).
Regrading claim 13, Grover discloses wherein the logic element of the computing cell comprises a NAND gate and the NAND gate receives a signal from a data output terminal of the memory element and the select signal (FIG 4-5; [0060] discloses computing operations including gating operation e.g., NAND gate and gate receiving inversed signal due to the NAND gating from 132 and 150).
Regrading claim 15, Grover discloses a method of reading data from an array of memory cells(FIG 4-5; reading data from 132), the method comprising: applying a select signal to a logic element(150 to 140), the logic element being responsive to the select signal and a signal from a respective memory cell (FIG 4-5; [0060] discloses a logic element 140 coupled to 130 and receives select signal 150), wherein the memory cell is configured to store a bit of data and to output the bit of data when data are read from the memory cells(132 storing data and outputting when data is read from 132 to 160); and determining a data value associated with data stored in the memory cells based on a voltage of a bit line(FIG 4-5; [0072] discloses determining values individual bit values logic ones or zero, and any number of bias bitcells being grouped to select a suitable bias value of computing cells).
Regrading claim 16, Grover discloses further comprising storing data in each of the memory cells (132 storing data)
Regrading claim 20, Grover discloses memory device comprising: a storage element configured to store one bit of data and to output the bit of data when the bit of data is read from a memory cell(FIG 4; memory element 130 having bias elements arranged to perform particular computing operation within memory array 132(storing bit data)); and a logic gate configured to receive a signal that is a representation of the bit of data stored in the storage element and a select signal(FIG 4-5; [0060] discloses a logic element 140 coupled to 130 and receives select signal 150).
Claim(s) 20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Sunkavalli et al (US11194490).
Regarding claim 20, Sunkavalli discloses a memory cell comprising: a storage element configured to store one bit of data and to output the bit of data when the bit of data is read from a memory cell (FIG 4 & 7; col 4, line 3-45 MAC, systolic array 214 clearly shows data being outputted to memory, wherein MAC (values) storing and being therefrom and outputted to 310 and e.g., comprising channel 0 comprising storage storing data); and a logic gate configured to receive a signal that is a representation of the bit of data stored in the storage element and a select signal (FIG 7; 510 receiving data outputted from MAC at a first terminal and select signal at a second terminal).
Claim 20 is rejected under 35 U.S.C. 102a(1) as being anticipated by Hebig et al (US201700117034).
Regarding claim 20, Hebig discloses a memory cell comprising: a storage element configured to store one bit of data and to output the bit of data when the bit of data is read from a memory cel (FIG 5A; [0031] discloses 502.1 storing logic value); and a logic gate configured to receive a signal that is a representation of the bit of data stored in the storage element and a select signal(FIG 5A; logic gate 520 receiving at first terminal through 550 of logic value and select signal from the left side of the 520 line).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-11, 14, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grover et al in view of Rim et al (US20160042785).
Regrading claim 10, Grover discloses further comprising of the select signal(FIG 4; 150).
However, Grover does not disclose a pre-charge circuit configured to drive a bit line low prior to assertion the select signal.
In the same field of endeavor, Rim discloses a pre-charge circuit configured to drive a bit line low prior to assertion (FIG 4; [0071-0073] 220 pre charging BL prior to SEL signal enabled prior to a read operation e.g., unselected side).
Grover and Rim are analogous art because they are all directed to a memory device comprising memory array, sense amplifier and selecting signal, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Grover to include Rim because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Rim in the teachings of Grover for the benefits avoiding an increase in power consumptions of the memory device and increase in chip area {0006 Rim).
Regrading claim 11, Grover discloses wherein the computing cell is configured to drive a voltage of the bit line lower when the memory element contains a 1 data value and when the select signal is high (Rim FIG 4; [0073] discloses QB is logic low, bit line voltage VRBL 110 is high, SEL1 is high).
Regrading claim 14, Grover discloses further comprising a pre-charge circuit configured to drive a bit line high prior to assertion of the select signal (Rim FIG 4; (FIG 4; [0071-0073] 220 pre charging BL high prior to SEL signal enabled prior to a read operation e.g., selected side).
Regrading claim 18, Grover discloses and the particular memory cell stores a predetermined data value (FIG 4; [0060] discloses information stored in one or more bias circuits 148 being use as operand data in computing operation e.g., predetermined).
However, Grover does not disclose wherein a particular memory cell drives the bit line away from a precharged level of the bit line when the select signal is active
Rim discloses wherein a particular memory cell drives the bit line away from a precharged level of the bit line when the select signal is active (Rim FIG 4; (FIG 4; [0071-0073] 220 driving away from pre charging BL when SEL1 e.g., is high).
Regrading claim 19, Grover discloses wherein the data value indicates a number of memory cells having a predetermined data value (FIG 4-5; [0072] discloses determining values individual bit values logic ones or zero (based on determined pre-data stored in 148), and any number of bias bitcells
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chung et al (US20190392896 FIG 5c2 discloses storage device 512 connected to logic unit 540 and capacitor 535 connected to bit line BL0).
Hokenmaier et al (US10360971 FIG 10 discloses 1-bit storage REG connected to logic unit N).
Knag et al (US20190102359 FIG 4; discloses logic unit Xo connected to storage unit Woo).
Beer et al (US6737695 FIG 1, Zimmer et al (US8861290 FIG 2A) & Park et al (US9734910 FIG 12).
Asenov et al (US9324392 FIG 6; discloses logic units 550, 552 and 554 receiving an WA_EN signal and outputting data to capacitor 555 connected to bit line).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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