Prosecution Insights
Last updated: October 23, 2026
Application No. 18/967,855

CIRCUIT BOARD

Non-Final OA §102
Filed
Dec 04, 2024
Priority
May 21, 2020 — RE 10-2020-0060679 +2 more
Examiner
NORRIS, JEREMY C
Art Unit
Tech Center
Assignee
LG Innotek Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
875 granted / 1008 resolved
+26.8% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
16 currently pending
Career history
1027
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
42.6%
+2.6% vs TC avg
§102
51.0%
+11.0% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1008 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 7, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 205/0083469 A1 (Sunohara). Sunohara discloses, referring primarily to figures 1-6, a circuit board comprising: an insulating layer (11, 12) including a via hole (11x) passing through an upper surface and a lower surface opposite to the upper surface; a through via (15, 25) disposed in the via hole; and a metal layer (13, 14) disposed between an inner wall of the via hole and a side surface of the through via, wherein a thickness of the metal layer in a horizontal direction changes from the upper surface of the insulating layer toward the lower surface of the insulating layer ([0045]) [claim 1], wherein the thickness of the metal layer in the horizontal direction decreases toward the lower surface of the insulating layer ([0045]) [claim 2], wherein the metal layer includes: a first metal layer (13) in contact with the inner wall of the via hole; and a second metal layer (14) disposed between the first metal layer and the side surface of the through via [claim 3], wherein the first metal layer and the second metal layer include different metal materials ([0046]) [claim 4], wherein a thickness of the first metal layer in the horizontal direction decreases toward the lower surface of the insulating layer ([0045]) [claim 7], wherein a thickness of the second metal layer in the horizontal direction decreases toward the lower surface of the insulating layer ([0045]) [claim 8]. Claim(s) 1, 3, 4, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2006/0144618 A1 (Song). Song discloses, referring primarily to figures 7a-7g, a circuit board comprising: an insulating layer (71) including a via hole (73) passing through an upper surface and a lower surface opposite to the upper surface; a through via (77) disposed in the via hole; and a metal layer (74, 75) disposed between an inner wall of the via hole and a side surface of the through via, wherein a thickness of the metal layer in a horizontal direction changes from the upper surface of the insulating layer toward the lower surface of the insulating layer ([0063]) [claim 1], wherein the metal layer includes: a first metal layer (74) in contact with the inner wall of the via hole; and a second metal layer (75) disposed between the first metal layer and the side surface of the through via [claim 3], wherein the first metal layer and the second metal layer include different metal materials ([0051]) [claim 4], further comprising: an upper circuit layer disposed on the upper surface of the insulating layer; and a lower circuit layer disposed on the lower surface of the insulating layer (72) [claim 10]. Allowable Subject Matter Claims 5, 6, 9, and 11-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 5 states the limitation “wherein the through via includes a metal material different from the metal materials of the first metal layer and the metal material of the first metal layer.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claim 6 states the limitation “wherein the first metal layer includes palladium, and the second metal layer includes gold.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claim 9 states the limitation “wherein the through via has a slope in which a width in the horizontal direction decreases toward the lower surface of the insulating layer.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claims 11-19 state the limitation “wherein the upper circuit layer protrudes on the insulating layer, and wherein the lower circuit layer is embedded in the insulating layer.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JEREMY C. NORRIS Examiner Art Unit 2847 /JEREMY C NORRIS/ Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Dec 04, 2024
Application Filed
Oct 06, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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4y 11m to grant Granted Oct 20, 2026
Patent 12772377
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2y 6m to grant Granted Oct 20, 2026
Patent 12764864
CURRENT SENSOR FOR A PRINTED CIRCUIT BOARD
2y 8m to grant Granted Oct 13, 2026
Patent 12757317
TECHNOLOGIES FOR REDUCING THE IMPACT OF RADIOFREQUENCY INTERFERENCE ON A CIRCUIT BOARD
2y 10m to grant Granted Oct 06, 2026
Patent 12757334
CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 4m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
91%
With Interview (+4.3%)
2y 4m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1008 resolved cases by this examiner. Grant probability derived from career allowance rate.

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