Prosecution Insights
Last updated: April 19, 2026
Application No. 18/967,997

DISPLAY DEVICE

Non-Final OA §103
Filed
Dec 04, 2024
Examiner
ADEDIRAN, ABDUL-SAMAD A
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
2y 1m
To Grant
92%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
481 granted / 617 resolved
+16.0% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
22 currently pending
Career history
639
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
41.2%
+1.2% vs TC avg
§102
19.5%
-20.5% vs TC avg
§112
29.0%
-11.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 617 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 13, 2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 16-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Choi, in view of Hong et al., U.S. Patent Application Publication 2006/0256103 A1 (hereinafter Hong), Kang et al., U.S. Patent Application Publication 2023/0389368 A1 (hereinafter Kang), Park et al., U.S. Patent Application Publication 2014/0118221 A1 (hereinafter Park I), Kwon, U.S. Patent Application Publication 2017/0117342 A1 (hereinafter Kwon), and Jung et al., U.S. Patent Application Publication 2005/0030254 A1 (hereinafter Jung). Regarding claim 16, Choi teaches a display device (DP FIG. 3, paragraph[0089] of Choi teaches FIG. 3 is a plan view of a display panel DP according to an embodiment of the present disclosure (i.e., Choi teaches a display panel divided into distinct areas)), comprising: a first display panel including a first pixel; a second display panel including a second pixel (DA1, BA, and AA2, PX; DA1 and FA0, PX FIGS. 1A-3, paragraphs[0093]-[0094] of Choi teaches the display area DP-DA may include two first display areas DA1 corresponding to the first non-folding area NFA10 and the second non-folding area NFA20, respectively, and a second display area DA2 corresponding to the folding area FA0; a length (e.g., a width) of the bending area BA and the second area AA2 in the first direction DR1 may be smaller than that of the first area AA1; and an area in which the length in a bending axis direction is shorter may be bent more easily, and See also at least paragraphs[0068]-[0076], [0089]-[0095], and [0255] of Choi (i.e., Choi teaches an electronic device that includes a display panel that includes a display area having a first display area with pixels along with a bending area and a second area, as well as a second display area with pixels along with a folding area, wherein the first display area and second display area are capable of displaying an image while being in an unfolded state opposite each other and capable of being in a folded state facing each other)); a first gate driver that (SDV FIGS. 1A-3, paragraphs[0090] of Choi teaches referring to FIG. 3, the display surface DS may include the display area DP-DA, and the non-display area DP-NDA around (e.g., adjacent to or surrounding around a periphery of) the display area DP-DA; pixels PX are disposed at (e.g., in or on) the display area DP-DA; a scan driving unit (e.g., a scan driver) SDV, a data driving unit (e.g., a data driver), and an emission driving unit (e.g., an emission driver) EDV may be disposed at (e.g., in or on) the non-display area DP-NDA; and the data driving unit may be a partial circuit configured in the driving chip DIC shown in FIG. 3, and See also at least paragraphs[0068]-[0076], [0089], [0091]-[0095], and [0255] of Choi (i.e., Choi teaches an electronic device that includes a display panel that includes a display area having a first display area with pixels along with a bending area and a second area, as well as a second display area with pixels along with a folding area, wherein the first display area and second display area are capable of displaying an image while being in an unfolded state opposite each other and capable of being in a folded state facing each other)); and a driving circuit that:; to a data line connected to the first pixel and the second pixel and (DIC FIGS. 1A-3, paragraphs[0095]-[0096] of Choi teaches the display panel DP may include the plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to Elm, first and second control lines CSL1 and CSL2, a power line PL, and a plurality of pads PD; here, m and n are natural numbers; the pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to Elm; the scan lines SL1 to SLm may extend in the first direction DR1 to be connected to the scan driver SDV; the data lines DL1 to DLn may extend in the second direction DR2 to be connected to the data driver DIC via the bending area BA; and the emission lines EL1 to Elm may extend in the first direction DR1 to be connected to the emission driving unit EDV, and See also at least paragraphs[0083]-[0084], [0090], [0096], [0099], and [0255] of Choi (i.e., Choi teaches a data chip, which has a data driving unit, connected to data lines that are connected to the pixels wherein the data lines extend through an bending area)); but does not expressly teach provides a first gate signal to a first gate line connected to the first pixel; a second gate driver that provides a second gate signal to a second gate line connected to the second pixel; provides a data voltage; provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines. However, Hong teaches provides first a gate signal to a first gate line connected to the first pixel (130 FIG. 1, paragraph[0033] of Hong teaches the first scan driving circuit 106 transmits first scan signals to the first cathode electrode layers 112 through first scan lines 130, and See also at least paragraphs[0028]-[0029] of Hong (i.e., Hong teaches a first scan driving circuit that transmits first scan signals to first cathode electrode layers that are included in first pixels)); a second gate driver that provides s second gate signal to a second gate line connected to the second pixel (108, 132 FIG. 1, paragraph[0034] of Hong teaches the second scan driving circuit 108 transmits second scan signals to the second cathode electrode layers 118 through second scan lines 132, and See also at least paragraph[0030] of Hong (i.e., Hong teaches a second scan driving circuit that transmits second scan signals to first cathode electrode layers that are included in second pixels));; but the combination of Choi and Hong still do not expressly teach provides a data voltage; provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines. However, Kang teaches provides a data voltage (FIGS. 7, paragraph[0118] of Kang teaches the data driver DDV may generate a plurality of data voltages, which correspond to the image signals, in response to the data control signal; the data voltages may be applied to the pixels PX through the data lines DL1-DLn; the emission driver EDV may generate a plurality of emission signals in response to the emission control signal; and the emission signals may be applied to the pixels PX through the emission lines EL1-ELm, and See also at least paragraphs[0100]-[0105], and [0115]-[0117] of Kang (i.e., Kang teaches a data driver that generates a plurality of data voltages, which correspond to image signals, wherein the data voltages are applied to pixels, which are within a display region, through data lines connected that are connected to the pixels)); and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines (PF FIGS. 3 and 7, paragraph[0080] of Kang teaches the panel protection film PF may be disposed below (e.g., underneath) the display panel DP; the panel protection film PF may protect a bottom portion of the display panel DP; and the panel protection film PF may be formed of or may include a flexible plastic material (e.g., such as polyethylene terephthalate (PET)), and See also at least paragraphs[0071]-[0079], [0081]-[0083], and [0100]-[0119] of Kang (i.e., Kang teaches a panel protection film capable of protecting data lines a control line connected to a scan driver)); but the combination of Choi, Hong, and Kang still do not expressly teach provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver. However, Park I provides (FIGS. 1-3, paragraph[0045] of Park I teaches the first scan driver 112 is connected to the driving chip 310 through a first scan connection line 10, and the first light emission control driver 113 is connected to the driving chip 310 through a first light emission control connection line 30; also, the second scan driver 122 is connected to the first scan driver 112 through a second scan connection line 20, and the second scan driver 122 is again connected to the driving chip 310 through the first scan driver 112 and the first scan connection line 10; further, the second light emission control driver 123 is connected to the first light emission control driver 113 through a second light emission control connection line 40, and the second light emission control driver 123 is again connected to the driving chip 310 through the first light emission control driver 113 and the first light emission control connection line 30; and the second scan driver 122 or the second light emission control driver 123 may be directly connected to the driving chip 310 through an additional signal line, and See also at least paragraphs[0051]-[0054], and [0058] of Park I (i.e., Park I teaches a driving chip that is capable of independently controlling, via a first scan connection line and a second scan connection line, driving of a first display panel and a second display panel respectively to independently or simultaneously display an image)); but the combination of Choi, Hong, Kang, and Park I still do not expressly teach a gate control signal to gate control lines connected to the first gate driver and the second gate driver. However, Kwon teaches a gate control signal to (FIGS. 25, paragraph[0117] of Kwon teaches the controller 140 can control the operations of the first gate driver GD1 and the second gate driver GD2 based on the status of the device, such as whether or not the display panel is folded, the positions of the areas, or so on, and See also at least paragraphs[0040], and [0112]-[0116] of Kwon (i.e., Kwon teaches the area of a foldable display panel are capable of being independently controlled, and even controlled based on whether or not the display panel is folded wherein a controller controls operations of a first gate driver for a first display area as well as operations of a second gate driver for a second display area based on a status of whether the display panel is folded or at least positions of the areas, and wherein the controller outputs a variety of gate control signals)); but the combination of Choi, Hong, Kang, Park I, and Kwon still do not expressly teach gate control lines connected to the first gate driver and the second gate driver. However, Jung teaches gate control lines connected to the first gate driver and the second gate driver (FIGS. 9 and 11, paragraphs[0097]-[0098] of Jung teaches referring back to FIGS. 9 and 11, the first gate signal output terminal OT.sub.2 is electrically connected to the first gate driver 240c at the second sub-region SA2, so that the first vertical control signal VCS1 is applied to the first gate driver 240c; the first gate driver 240c applies the first gate signal to the first gate lines GL1-1 to GL1-n in response to the first vertical control signal VCS1; the second gate signal output terminal OT3 is electrically connected to the second gate driver 310c via the second connection line CL2 formed on the third sub-region SA3 and the second flexible printed circuit board 350; thus, the second vertical control signal VCS2 is applied to the second gate driver 310c; and the second gate driver 310c applies the second gate signal to the second gate lines GL2-1 to GL2-i in response to the second vertical control signal VCS2 (i.e., Jung teaches a first gate driver and a second gate driver each connected to a respective connection line)). Furthermore, Choi, Hong, Kang, Park I, Kwon, and Jung are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of forming the display device with suitable distinct display regions. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of Choi based on Hong, Kang, Park I, Kwon, and Jung to have the first gate driver that provides a first gate signal to a first gate line connected to the first pixel; a second gate driver that provides a second gate signal to a second gate line connected to the second pixel; provide a data voltage; provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines. One reason for the modification as taught by Hong is to have a suitable dual panel apparatus including two panels capable of being driven simultaneously (paragraph[0002] of Hong). Another reason for the modification as taught by Kang is to have a display device that is capable of preventing a folding portion from being damaged (paragraph[0007] of Kang). Still another reason for the modification as taught by Park I is to have a suitable two side display device (ABSTRACT and paragraph[0003] of Park I). Moreover, another reason for the modification as taught by Kwon is to have a display panel divided into two areas having different light-emitting directions (paragraph[0009] of Kwon). Still moreover, another reason for the modification as taught by Jung is to have a display device with high resolution without significant increase in driver chip size (ABSTRACT, and paragraphs[0003] and [0010] of Jung). The same motivation and rationale to combine for claim 16 mentioned above, in light of corresponding statement of grounds of rejection, applies to each corresponding dependent claim mentioned in the corresponding statement of grounds of rejection. Regarding claim 17, Choi, Hong, Kang, Park I, Kwon, and Jung teach the display device of claim 16, wherein the first display panel includes: a main area that is configured to display an image; and a sub-area in which the driving circuit is disposed (DA1, BA, and AA2 FIGS. 1A-3, paragraphs[0093]-[0094] of Choi teaches the display area DP-DA may include two first display areas DA1 corresponding to the first non-folding area NFA10 and the second non-folding area NFA20, respectively, and a second display area DA2 corresponding to the folding area FA0; a length (e.g., a width) of the bending area BA and the second area AA2 in the first direction DR1 may be smaller than that of the first area AA1; and an area in which the length in a bending axis direction is shorter may be bent more easily, and See also at least paragraphs[0068]-[0076], [0083]-[0084], [0089]-[0092], [0096], [0099], and [0255] of Choi (i.e., Choi teaches an electronic device that includes the display panel that includes the display area having the first display area with pixels along with a bending area and a second area that has a data driver, wherein the first display area is capable of displaying the image while being in an unfolded state opposite)). Regarding claim 18, Choi, Hong, Kang, Park I, Kwon, and Jung teach the display device of claim 16, wherein the second display panel includes: a main area that is configured to display an image; and a sub-area connecting the main area and the first display panel, wherein the data line is disposed in the sub-area (DA1 and FA0 FIGS. 1A-3, and 5C, paragraphs[0093]-[0094] of Choi teaches the display area DP-DA may include two first display areas DA1 corresponding to the first non-folding area NFA10 and the second non-folding area NFA20, respectively, and a second display area DA2 corresponding to the folding area FA0; a length (e.g., a width) of the bending area BA and the second area AA2 in the first direction DR1 may be smaller than that of the first area AA1; and an area in which the length in a bending axis direction is shorter may be bent more easily, and See also at least paragraphs[0068]-[0076], [0089]-[0096], [0133], and [0255] of Choi (i.e., Choi teaches an electronic device that includes a display panel that includes a display area having a first display area with pixels along with a bending area and a second area, as well as a second display area with pixels along with a folding area, wherein the folding area directly interposes the first display area and second display area that are capable of displaying an image while being in an unfolded state opposite each other and capable of being in a folded state facing each other, and wherein the data lines extend through the folding area that has flexibility)). Regarding claim 19, Choi, Hong, Kang, Park I, Kwon, and Jung teach wherein the driving circuit is configured to: simultaneously display an image on the first display panel and the second display panel during the first mode; and (FIG. 1, paragraph[0051] of Park I teaches accordingly, the driving chip 310 may independently control the driving of the first display panel 210 and the second display panel 220; and accordingly, the first display panel 210 and the second display panel 220 may independently or simultaneously display the image, and See also at least paragraphs[0049]-[0050] (i.e., Park I teaches a driving chip that controls driving of a first display panel and a second display panel that simultaneously display an image)); but does not expressly teach display the image on one of the first display panel and the second display panel during the second mode. However, Kwon teaches display the image on one of the first display panel and the second display panel during the second mode (FIGS. 25, paragraph[0117] of Park I teaches the controller 140 can control the operations of the first gate driver GD1 and the second gate driver GD2 based on the status of the device, such as whether or not the display panel is folded, the positions of the areas, or so on, and See also at least paragraphs[0112]-[0116] of Kwon (i.e., Kwon teaches the area of a foldable display panel are capable of being independently controlled, and even controlled based on whether or not the display panel is folded wherein a controller controls operations of a first gate driver for a first display area as well as operations of a second gate driver for a second display area based on a status of whether the display panel is folded or at least positions of the areas)). Regarding claim 21, Choi teaches an electronic device, comprising: a display device (DP FIGS. 2-3, paragraph[0089] of Choi teaches FIG. 3 is a plan view of a display panel DP according to an embodiment of the present disclosure, and See also at least paragraphs[0077]-[0080] of Choi (i.e., Choi teaches an electronic device having that includes a display device having display module that includes a display panel divided into distinct areas)), comprising: a first display panel including a first pixel; a second display panel including a second pixel (DA1, BA, and AA2, PX; DA1 and FA0, PX FIGS. 1A-3, paragraphs[0093]-[0094] of Choi teaches the display area DP-DA may include two first display areas DA1 corresponding to the first non-folding area NFA10 and the second non-folding area NFA20, respectively, and a second display area DA2 corresponding to the folding area FA0; a length (e.g., a width) of the bending area BA and the second area AA2 in the first direction DR1 may be smaller than that of the first area AA1; and an area in which the length in a bending axis direction is shorter may be bent more easily, and See also at least paragraphs[0068]-[0076], [0089]-[0095], and [0255] of Choi (i.e., Choi teaches an electronic device that includes a display panel that includes a display area having a first display area with pixels along with a bending area and a second area, as well as a second display area with pixels along with a folding area, wherein the first display area and second display area are capable of displaying an image while being in an unfolded state opposite each other and capable of being in a folded state facing each other)); a first gate driver that (SDV FIGS. 1A-3, paragraphs[0090] of Choi teaches referring to FIG. 3, the display surface DS may include the display area DP-DA, and the non-display area DP-NDA around (e.g., adjacent to or surrounding around a periphery of) the display area DP-DA; pixels PX are disposed at (e.g., in or on) the display area DP-DA; a scan driving unit (e.g., a scan driver) SDV, a data driving unit (e.g., a data driver), and an emission driving unit (e.g., an emission driver) EDV may be disposed at (e.g., in or on) the non-display area DP-NDA; and the data driving unit may be a partial circuit configured in the driving chip DIC shown in FIG. 3, and See also at least paragraphs[0068]-[0076], [0089], [0091]-[0095], and [0255] of Choi (i.e., Choi teaches an electronic device that includes a display panel that includes a display area having a first display area with pixels along with a bending area and a second area, as well as a second display area with pixels along with a folding area, wherein the first display area and second display area are capable of displaying an image while being in an unfolded state opposite each other and capable of being in a folded state facing each other)); and a driving circuit that:; to a data line connected to the first pixel and the second pixel and (DIC FIGS. 1A-3, paragraphs[0095]-[0096] of Choi teaches the display panel DP may include the plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to Elm, first and second control lines CSL1 and CSL2, a power line PL, and a plurality of pads PD; here, m and n are natural numbers; the pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to Elm; the scan lines SL1 to SLm may extend in the first direction DR1 to be connected to the scan driver SDV; the data lines DL1 to DLn may extend in the second direction DR2 to be connected to the data driver DIC via the bending area BA; and the emission lines EL1 to Elm may extend in the first direction DR1 to be connected to the emission driving unit EDV, and See also at least paragraphs[0083]-[0084], [0090], [0096], [0099], and [0255] of Choi (i.e., Choi teaches a data chip, which has a data driving unit, connected to data lines that are connected to the pixels)); but does not expressly teach provides a gate signal to a first gate line connected to the first pixel; a second gate driver that provides a second gate signal to a second gate line connected to the second pixel; provides a data voltage; provides a gate signal to a first gate line connected to the first pixel; a second gate driver that provides a second gate signal to a second gate line connected to the second pixel; provides a data voltage; provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines. However, Hong teaches provides first a gate signal to a first gate line connected to the first pixel (130 FIG. 1, paragraph[0033] of Hong teaches the first scan driving circuit 106 transmits first scan signals to the first cathode electrode layers 112 through first scan lines 130, and See also at least paragraphs[0028]-[0029] of Hong (i.e., Hong teaches a first scan driving circuit that transmits first scan signals to first cathode electrode layers that are included in first pixels)); a second gate driver that provides s second gate signal to a second gate line connected to the second pixel (108, 132 FIG. 1, paragraph[0034] of Hong teaches the second scan driving circuit 108 transmits second scan signals to the second cathode electrode layers 118 through second scan lines 132, and See also at least paragraph[0030] of Hong (i.e., Hong teaches a second scan driving circuit that transmits second scan signals to first cathode electrode layers that are included in second pixels));; but the combination of Choi and Hong still do not expressly teach provides a data voltage; provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines. However, Kang teaches provides a data voltage (FIGS. 7, paragraph[0118] of Kang teaches the data driver DDV may generate a plurality of data voltages, which correspond to the image signals, in response to the data control signal; the data voltages may be applied to the pixels PX through the data lines DL1-DLn; the emission driver EDV may generate a plurality of emission signals in response to the emission control signal; and the emission signals may be applied to the pixels PX through the emission lines EL1-ELm, and See also at least paragraphs[0100]-[0105], and [0115]-[0117] of Kang (i.e., Kang teaches a data driver that generates a plurality of data voltages, which correspond to image signals, wherein the data voltages are applied to pixels, which are within a display region, through data lines connected that are connected to the pixels)); and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines (PF FIGS. 3 and 7, paragraph[0080] of Kang teaches the panel protection film PF may be disposed below (e.g., underneath) the display panel DP; the panel protection film PF may protect a bottom portion of the display panel DP; and the panel protection film PF may be formed of or may include a flexible plastic material (e.g., such as polyethylene terephthalate (PET)), and See also at least paragraphs[0071]-[0079], [0081]-[0083], and [0100]-[0119] of Kang (i.e., Kang teaches a panel protection film capable of protecting data lines a control line connected to a scan driver)); but the combination of Choi, Hong, and Kang still do not expressly teach provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver. However, Park I provides (FIGS. 1-3, paragraph[0045] of Park I teaches the first scan driver 112 is connected to the driving chip 310 through a first scan connection line 10, and the first light emission control driver 113 is connected to the driving chip 310 through a first light emission control connection line 30; also, the second scan driver 122 is connected to the first scan driver 112 through a second scan connection line 20, and the second scan driver 122 is again connected to the driving chip 310 through the first scan driver 112 and the first scan connection line 10; further, the second light emission control driver 123 is connected to the first light emission control driver 113 through a second light emission control connection line 40, and the second light emission control driver 123 is again connected to the driving chip 310 through the first light emission control driver 113 and the first light emission control connection line 30; and the second scan driver 122 or the second light emission control driver 123 may be directly connected to the driving chip 310 through an additional signal line, and See also at least paragraphs[0051]-[0054], and [0058] of Park I (i.e., Park I teaches a driving chip that is capable of independently controlling, via a first scan connection line and a second scan connection line, driving of a first display panel and a second display panel respectively to independently or simultaneously display an image)); but the combination of Choi, Hong, Kang, and Park I still do not expressly teach a gate control signal to gate control lines connected to the first gate driver and the second gate driver. However, Kwon teaches a gate control signal to (FIGS. 25, paragraph[0117] of Kwon teaches the controller 140 can control the operations of the first gate driver GD1 and the second gate driver GD2 based on the status of the device, such as whether or not the display panel is folded, the positions of the areas, or so on, and See also at least paragraphs[0040], and [0112]-[0116] of Kwon (i.e., Kwon teaches the area of a foldable display panel are capable of being independently controlled, and even controlled based on whether or not the display panel is folded wherein a controller controls operations of a first gate driver for a first display area as well as operations of a second gate driver for a second display area based on a status of whether the display panel is folded or at least positions of the areas, and wherein the controller outputs a variety of gate control signals)); but the combination of Choi, Hong, Kang, Park I, and Kwon still do not expressly teach gate control lines connected to the first gate driver and the second gate driver. However, Jung teaches gate control lines connected to the first gate driver and the second gate driver (FIGS. 9 and 11, paragraphs[0097]-[0098] of Jung teaches referring back to FIGS. 9 and 11, the first gate signal output terminal OT.sub.2 is electrically connected to the first gate driver 240c at the second sub-region SA2, so that the first vertical control signal VCS1 is applied to the first gate driver 240c; the first gate driver 240c applies the first gate signal to the first gate lines GL1-1 to GL1-n in response to the first vertical control signal VCS1; the second gate signal output terminal OT3 is electrically connected to the second gate driver 310c via the second connection line CL2 formed on the third sub-region SA3 and the second flexible printed circuit board 350; thus, the second vertical control signal VCS2 is applied to the second gate driver 310c; and the second gate driver 310c applies the second gate signal to the second gate lines GL2-1 to GL2-i in response to the second vertical control signal VCS2 (i.e., Jung teaches a first gate driver and a second gate driver each connected to a respective connection line)). Furthermore, Choi, Hong, Kang, Park I, Kwon, and Jung are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of forming the display device with suitable distinct display regions. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of Choi based on Hong, Kang, Park I, Kwon, and Jung to have the first gate driver that provides a gate signal to a first gate line connected to the first pixel; a second gate driver that provides a second gate signal to a second gate line connected to the second pixel; provides a data voltage; provides a gate signal to a first gate line connected to the first pixel; a second gate driver that provides a second gate signal to a second gate line connected to the second pixel; provides a data voltage; provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines. One reason for the modification as taught by Hong is to have a suitable dual panel apparatus including two panels capable of being driven simultaneously (paragraph[0002] of Hong). Another reason for the modification as taught by Kang is to have a display device that is capable of preventing a folding portion from being damaged (paragraph[0007] of Kang). Still another reason for the modification as taught by Park I is to have a suitable two side display device (ABSTRACT and paragraph[0003] of Park I). Moreover, another reason for the modification as taught by Kwon is to have a display panel divided into two areas having different light-emitting directions (paragraph[0009] of Kwon). Still moreover, another reason for the modification as taught by Jung is to have a display device with high resolution without significant increase in driver chip size (ABSTRACT, and paragraphs[0003] and [0010] of Jung). Potentially Allowable Subject Matter Claim 1 is allowable, because the prior art references of record do not teach the combination of all element limitations as presently claimed. For example, in regard to claim 1 the prior art of record at least does not expressly teach concept of wherein the driving circuit includes the frame memory configured to store input image data for one of the first display panel and the second display panel, the frame memory having a capacity corresponding to at least a higher resolution of the first display panel and the second display panel. In addition, claims 2-15 are allowable, because for each of claims 2-15, at least in light of their dependency on their respective independent claim, the prior art references of record do not teach the combination of all element limitations as presently claimed. Response to Arguments Applicant's arguments filed January 13, 2026 have been fully considered but they are not persuasive. The following is a brief summary of Applicant’s arguments: In regard to currently amended claim 16, Applicants submitted that the prior art of record does not teach the following: “a driving circuit configured to: that provides a data voltage to a data line connected to the first pixel and the second pixel and provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data line and the gate control lines”. In regard to new claim 21, Applicants submitted that the prior art of record does not teach the following: “a driving circuit configured to: that provides a data voltage to a data line connected to the first pixel and the second pixel and provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data line and the gate control lines”. Examiner respectfully disagrees. Specifically, in regard to arguments ‘A’ and ‘B’ summarized above at least paragraphs[0095]-[0096] of Choi teaches the display panel DP may include the plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to Elm, first and second control lines CSL1 and CSL2, a power line PL, and a plurality of pads PD; here, m and n are natural numbers; the pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to Elm; the scan lines SL1 to SLm may extend in the first direction DR1 to be connected to the scan driver SDV; the data lines DL1 to DLn may extend in the second direction DR2 to be connected to the data driver DIC via the bending area BA; and the emission lines EL1 to Elm may extend in the first direction DR1 to be connected to the emission driving unit EDV, and See also at least paragraphs[0083]-[0084], [0090], [0096], [0099], and [0255] of Choi. Thus, Choi teaches a data chip, which has a data driving unit, connected to data lines that are connected to the pixels wherein the data lines extend through an bending area. In addition, paragraphs[0033]-[0034] of Hong teaches the first scan driving circuit 106 transmits first scan signals to the first cathode electrode layers 112 through first scan lines 130; and the second scan driving circuit 108 transmits second scan signals to the second cathode electrode layers 118 through second scan lines 132, and See also at least paragraphs[0028]-[0030] of Hong. Thus, Hong teaches a first scan driving circuit that transmits first scan signals to first cathode electrode layers that are included in first pixels, and a second scan driving circuit that transmits second scan signals to first cathode electrode layers that are included in second pixels. Still in addition, paragraph[0118] of Kang teaches the data driver DDV may generate a plurality of data voltages, which correspond to the image signals, in response to the data control signal; the data voltages may be applied to the pixels PX through the data lines DL1-DLn; the emission driver EDV may generate a plurality of emission signals in response to the emission control signal; and the emission signals may be applied to the pixels PX through the emission lines EL1-ELm, and See also at least paragraphs[0100]-[0105], and [0115]-[0117] of Kang. Thus, Kang teaches a data driver that generates a plurality of data voltages, which correspond to image signals, wherein the data voltages are applied to pixels, which are within a display region, through data lines connected that are connected to the pixels. Also, paragraph[0080] of Kang teaches the panel protection film PF may be disposed below (e.g., underneath) the display panel DP; the panel protection film PF may protect a bottom portion of the display panel DP; and the panel protection film PF may be formed of or may include a flexible plastic material (e.g., such as polyethylene terephthalate (PET)), and See also at least paragraphs[0071]-[0079], [0081]-[0083], and [0100]-[0119] of Kang. Thus, Kang teaches a panel protection film capable of protecting data lines a control line connected to a scan driver. Still also, paragraph[0045] of Park I teaches the first scan driver 112 is connected to the driving chip 310 through a first scan connection line 10, and the first light emission control driver 113 is connected to the driving chip 310 through a first light emission control connection line 30; also, the second scan driver 122 is connected to the first scan driver 112 through a second scan connection line 20, and the second scan driver 122 is again connected to the driving chip 310 through the first scan driver 112 and the first scan connection line 10; further, the second light emission control driver 123 is connected to the first light emission control driver 113 through a second light emission control connection line 40, and the second light emission control driver 123 is again connected to the driving chip 310 through the first light emission control driver 113 and the first light emission control connection line 30; and the second scan driver 122 or the second light emission control driver 123 may be directly connected to the driving chip 310 through an additional signal line, and See also at least paragraphs[0051]-[0054], and [0058] of Park I. Thus, Park I teaches a driving chip that is capable of independently controlling, via a first scan connection line and a second scan connection line, driving of a first display panel and a second display panel respectively to independently or simultaneously display an image. Moreover, paragraph[0117] of Kwon teaches the controller 140 can control the operations of the first gate driver GD1 and the second gate driver GD2 based on the status of the device, such as whether or not the display panel is folded, the positions of the areas, or so on, and See also at least paragraphs[0040], and [0112]-[0116] of Kwon. Thus, Kwon teaches the area of a foldable display panel are capable of being independently controlled, and even controlled based on whether or not the display panel is folded wherein a controller controls operations of a first gate driver for a first display area as well as operations of a second gate driver for a second display area based on a status of whether the display panel is folded or at least positions of the areas, and wherein the controller outputs a variety of gate control signals. Still moreover, paragraphs[0097]-[0098] of Jung teaches referring back to FIGS. 9 and 11, the first gate signal output terminal OT.sub.2 is electrically connected to the first gate driver 240c at the second sub-region SA2, so that the first vertical control signal VCS1 is applied to the first gate driver 240c; the first gate driver 240c applies the first gate signal to the first gate lines GL1-1 to GL1-n in response to the first vertical control signal VCS1; the second gate signal output terminal OT3 is electrically connected to the second gate driver 310c via the second connection line CL2 formed on the third sub-region SA3 and the second flexible printed circuit board 350; thus, the second vertical control signal VCS2 is applied to the second gate driver 310c; and the second gate driver 310c applies the second gate signal to the second gate lines GL2-1 to GL2-i in response to the second vertical control signal VCS2. Thus, Jung teaches a first gate driver and a second gate driver each connected to a respective connection line. Furthermore, as mentioned above, Choi, Hong, Kang, Park I, Kwon, and Jung are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of forming the display device with suitable distinct display regions. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of Choi based on Hong, Kang, Park I, Kwon, and Jung to have the first gate driver that provides a first gate signal to a first gate line connected to the first pixel; a second gate driver that provides a second gate signal to a second gate line connected to the second pixel; provide a data voltage; provides a gate control signal to gate control lines connected to the first gate driver and the second gate driver; and a bending protective layer that is disposed on the first display panel and the second display panel and protects the data lines and the gate control lines. One reason for the modification as taught by Hong is to have a suitable dual panel apparatus including two panels capable of being driven simultaneously (paragraph[0002] of Hong). Another reason for the modification as taught by Kang is to have a display device that is capable of preventing a folding portion from being damaged (paragraph[0007] of Kang). Still another reason for the modification as taught by Park I is to have a suitable two side display device (ABSTRACT and paragraph[0003] of Park I). Moreover, another reason for the modification as taught by Kwon is to have a display panel divided into two areas having different light-emitting directions (paragraph[0009] of Kwon). Still moreover, another reason for the modification as taught by Jung is to have a display device with high resolution without significant increase in driver chip size (ABSTRACT, and paragraphs[0003] and [0010] of Jung). Also, in regard to independent claim 16 Applicant submitted that similar arguments apply to independent claim 21 and respective dependent claims. Therefore, the Examiner’s response in regard to arguments ‘A’ and ‘B’ summarized above, also applies to the independent claim 21 and the respective dependent claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDUL-SAMAD A ADEDIRAN whose telephone number is (571)272-3128. The examiner can normally be reached Monday through Thursday, 8:00 am to 5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABDUL-SAMAD A ADEDIRAN/Primary Examiner, Art Unit 2621
Read full office action

Prosecution Timeline

Dec 04, 2024
Application Filed
Aug 01, 2025
Non-Final Rejection — §103
Sep 24, 2025
Applicant Interview (Telephonic)
Sep 24, 2025
Examiner Interview Summary
Nov 03, 2025
Response Filed
Nov 16, 2025
Final Rejection — §103
Jan 13, 2026
Response after Non-Final Action
Feb 12, 2026
Request for Continued Examination
Feb 20, 2026
Response after Non-Final Action
Mar 06, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604613
DISPLAY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12592188
PIXEL CIRCUITS AND DISPLAY PANELS
2y 5m to grant Granted Mar 31, 2026
Patent 12586527
PIXEL DRIVING CIRCUIT, DISPLAY DEVICE INCLUDING THE SAME, AND METHOD FOR DRIVING THE DISPLAY DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12586496
DISPLAY DEVICE AND METHOD OF DRIVING A DISPLAY DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12572202
Determining IPD By Adjusting The Positions Of Displayed Stimuli
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
92%
With Interview (+13.9%)
2y 1m
Median Time to Grant
High
PTA Risk
Based on 617 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month