DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
On 06/23/2026, a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ 05/22/2026 response has been entered.
Summary of Response
Applicant’s 05/22/2026 response includes: (a) claims 1-2, 4, 6, 8, 11-12, 16-17, 22, 24 and 26 are currently amended; (b) claims 3 and 9-10 are previously presented; (c) claims 5, 7, 13-15, 18-21 and 23-25 are original; and (d) the grounds for rejection set forth in the 03/24/2026 office action are traversed. Claims 1-26 are currently pending and an office action follows:
Response to Arguments
Applicant’s arguments filed with respect to the rejection of claims 1-15 and 21-24 have been fully considered and are persuasive. Thus, these claims are allowed. However, these arguments are not persuasive as to claims 16-19 and 25-26. As to independent claim 16, applicant argues that Kim in view of Kim II does not teach a a first voltage transfer line in the form of a power line disposed between the sixth data line DL6 and the seventh data line DL7 (05/22/2026 response, p. 9). Examiner points out that applicant’s interpretation of claim 16 is a red herring, because it does not refer to the actual claim language, which includes the first voltage transfer line being between the sixth data line and the first data line. Thus, claim 16 teaches:
one of the first voltage transfer lines(for each PXL: a vertical line providing ELVDD)(FIG. 4; ¶0034) is disposed between the sixth data line(DL6)(FIGs. 1-2; ¶0031) of one(DL4-DL6)(FIGs. 1-2; ¶0031) of the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2; ¶0031) and the first data line(DL1)(FIGs. 1-2; ¶0031 – FIG. 4 depicts a vertical line providing ELVDD is on PXL’s left side and Vdata is on its right side, and thus any one of the vertical lines providing ELVDD to a PXL in the 2nd through 6th columns of PXL is a first voltage transfer line between 1st and 6th data lines.) of a first group(DL1-DL3)(FIGs. 1-2; ¶0031) neighboring the one(DL4-DL6)(FIGs. 1-2; ¶0031) of the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2; ¶0031).
Applicant also argues that Kim in view of Kim II does not teach an ELVDD line between two facing data lines (05/22/2026 response, p. 9). Examiner notes that while facing data lines is included in the other allowed independent claims, it is not included in claim 16.
Claim Rejections – 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
6. Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2016/0019842 A1 to Kim in view of U.S. Patent Pub. No. 2019/0080651 A1 to Kim et al. (“Kim II”).
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As to claim 16, Kim discloses a display apparatus (FIG. 1; ¶0030) comprising:
a display (FIGs. 1-2: DSP; ¶¶0030-0031) comprising sub-pixel circuits(R, G, B)(FIGs. 2, 5: PGO-PGE; ¶¶0031, 0033) arranged in a row direction and a column direction (FIGs. 2, 5: PGO-PGE, R, G, B; ¶¶0031, 0033), data lines(DL1-DLj)(FIGs. 1-2; ¶0031) connected to corresponding sub-pixel circuits(R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047), and first voltage transfer lines(for each PXL: a vertical line providing ELVDD)(FIG. 4; ¶0034) extending in the column direction (FIG. 4: for each PXL an ELVDD line; ¶0034);
a data driving circuit(DD)(FIGs. 1, 5; ¶0031) that outputs a data signal through output lines(OC1-OC6 and/or pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073);
a data distributor(D-MUX)(FIGs 1, 5; ¶0075) selectively connecting each of the output lines(OC1-OC6 and/or pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073) to one of(one of: DL1/DL4, DL2/DL5, DL3/DL6, DL7/DL10, D8/D11, D9/D12)(FIGs. 1-2, 5; ¶0077) a corresponding pair of data lines(DL1/DL4, DL2/DL5, DL3/DL6, DL7/DL10, D8/D11, D9/D12)(FIGs. 1-2, 5; ¶0077) among the data lines(DL1-DLj)(FIGs. 1-2, 5; ¶0031) according to a first control signal(CS1)(FIG. 5; ¶0068) and a second control signal(CS2)(FIG. 5; ¶0068); and
a control circuit(D-MUX, CL1)(FIG. 5; ¶0068) that alternately outputs the first control signal(CS1)(FIG. 5; ¶0068) and the second control signal(CS2)(FIG. 5; ¶0068), wherein
the data lines(DL1-DLj)(FIGs. 1-2; ¶0031) comprise first groups(DL1-DL3, DL7-DL9)(FIGs. 1-2; ¶0031) and second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2; ¶0031),
each of the first groups(DL1-DL3, DL7-DL9)(FIGs. 1-2; ¶0031) comprises a first data line(DL1, DL7)(FIGs. 1-2; ¶0031), a second data line(DL2, DL8)(FIGs. 1-2; ¶0031), and a third data line(DL3, DL9)(FIGs. 1-2; ¶0031) that are sequentially arranged in the row direction (FIGs. 1-2: DL1-DL3, DL7-DL9; ¶0031) and that are connected to a corresponding one of the output lines(OC1-OC6 and/or pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073) according to the first control signal(CS1)(FIG. 5; ¶0068),
each of the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2; ¶0031) comprises a fourth data line(DL4, DL10)(FIGs. 1-2; ¶0031), a fifth data line(DL5, DL11)(FIGs. 1-2; ¶0031), and a sixth data line(DL6, DL12)(FIGs. 1-2; ¶0031) that are sequentially arranged in the row direction (FIGs. 1-2: DL4-DL6, DL10-DL12; ¶0031) and that are connected to a corresponding one of the output lines(OC1-OC6 and/or pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073) according to the second control signal(CS21)(FIG. 5; ¶0068),
the first groups(DL1-DL3, DL7-DL9)(FIGs. 1-2; ¶0031) and the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2; ¶0031) are alternately arranged in the row direction (FIGs. 1-2: DL1-DL3, DL4-DL6, DL7-DL9, DL10-DL12; ¶0031),
one of the first voltage transfer lines(for each PXL: a vertical line providing ELVDD)(FIG. 4; ¶0034) is disposed between the sixth data line(DL6)(FIGs. 1-2; ¶0031) of one(DL4-DL6)(FIGs. 1-2; ¶0031) of the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2; ¶0031) and the first data line(DL1)(FIGs. 1-2; ¶0031 – FIG. 4 depicts a vertical line providing ELVDD is on PXL’s left side and Vdata is on its right side, and thus any one of the vertical lines providing ELVDD to a PXL in the 2nd through 6th columns of PXL is a first voltage transfer line between 1st and 6th data lines.) of a first group(DL1-DL3)(FIGs. 1-2; ¶0031) neighboring the one(DL4-DL6)(FIGs. 1-2; ¶0031) of the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2; ¶0031),
and sub-pixel circuits(R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047) arranged in even-numbered sub-pixel circuit columns(even numbered ones of 1-12 columns of R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047), and
sub-pixel circuits(R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047) arranged in odd-numbered sub-pixel circuit columns(odd numbered ones of 1-12 columns of R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047) have a non-flipped shape (FIGs. 2, 4, 5: odd numbered ones of 1-12 columns of R, G, B, PGO-PGE; ¶¶0031, 0033, 0035, 0047).
Kim does not expressly disclose and sub-pixel circuits arranged in even-numbered sub-pixel circuit columns have a flipped shape.
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Kim II discloses and pixel circuits arranged in even-numbered pixel circuit columns have a flipped shape (FIG. 5; ¶¶0073, especially – “the dummy pixel PD in some embodiments may be omitted”, 0094, 0129 - even-numbered pixels are flipped with respect to odd-numbered pixels. Also, dummy pixels PD and dummy data lines D0 may be omitted).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim with Kim II to provide a display apparatus that is brighter by having a higher aspect ratio (i.e., Kim discloses spacing on either side of each data line in the display area which is modified by Kim II so that a space on sides of two data lines is shared).
Kim and Kim II teach and sub-pixel circuits arranged in even-numbered sub-pixel circuit columns have a flipped shape (Kim: FIGs. 2, 4, 5: even numbered ones of 1-12 columns of R, G, B, PGO-PGE; ¶¶0031, 0033, 0035, 0047; Kim II: FIG. 5; ¶¶0073, 0094, 0129).
As to claim 17, Kim and Kim II teach the display apparatus of claim 16, as applied above but does not disclose the above underlined limitations.
Kim and Kim II further teach wherein each of the data lines (Kim: FIGs. 1-2, 5: DL1-DLj; ¶0031; Kim II: D1-D16; ¶0071) is arranged on either a first side(right side) or a second side(left side) of a corresponding sub-pixel circuit column(Kim: FIGs. 2, 5: PGO-PGE, one of: column of Rs, column of Gs, column of Bs; ¶¶0031, 0033; Kim: FIG. 5: ¶¶0071, 0073), each of odd-numbered data lines is arranged on the first side of the corresponding sub-pixel circuit column (Kim: FIGs. 1-2, 5: FIGs. 2, 5: PGO-PGE, odd numbered ones of: DL1-DLj, one of: column of Rs, column of Gs, column of Bs; ¶¶0031, 0033; Kim II: FIG. 5: odd numbered ones of D1-D16 are arranged on the right side of a corresponding pixel to its left; ¶0071), and each of even-numbered data lines is arranged on the second side of the corresponding sub-pixel circuit column (Kim: FIGs. 1-2, 5: FIGs. 2, 5: PGO-PGE, even numbered ones of: DL1-DLj, one of: column of Rs, column of Gs, column of Bs; ¶¶0031, 0033; Kim II: FIG. 5: even numbered ones of D1-D16 are arranged on the left side of a corresponding pixel to its left; ¶0071).
The motivation to combine the additional teachings of Kim II is for the same reasoning set forth above for claim 19.
As to claim 18, Kim and Kim II teach the display apparatus of claim 16, as applied above.
Kim further discloses wherein the first data line(DL1)(FIGs. 1-2; ¶0031) is connected to a first output line(left one of pair of lines directly connected to OC1)(FIGs. 1, 5; ¶0073) from among the output lines(pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073) according to the first control signal(CS1)(FIG. 5; ¶¶0045, 0068, 0073),
the second data line(DL2)(FIGs. 1-2; ¶0031) is connected to a second output line(left one of pair of lines directly connected to OC2)(FIGs. 1, 5; ¶0073) from among the output lines(pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073) according to the first control signal(CS1)(FIG. 5; ¶¶0045, 0068, 0073),
the third data line(DL3)(FIGs. 1-2; ¶0031) is connected to a third output line(left one of pair of lines directly connected to OC3)(FIGs. 1, 5; ¶0073) from among the output lines(pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073) according to the first control signal(CS1)(FIG. 5; ¶¶0045, 0068, 0073),
the fourth data line(DL4)(FIGs. 1-2; ¶0031) is connected to the first output line(left one of pair of lines directly connected to OC1)(FIGs. 1, 5; ¶0073) according to the second control signal(CS2)(FIG. 5; ¶¶0045, 0068, 0073 – DL4 is coupling connected to the left on of pair of lines directly connected to OC1 via CS2),
the fifth data line(DL5)(FIGs. 1-2; ¶0031) is connected to the second output line(left one of pair of lines directly connected to OC2)(FIGs. 1, 5; ¶0073) according to the second control signal(CS2)(FIG. 5; ¶¶0045, 0068, 0073 – DL5 is coupling connected to the left one of pair of lines directly connected to OC2 via CS2), and
the sixth data line(DL6)(FIGs. 1-2; ¶0031) is connected to the third output line(left one of pair of lines directly connected to OC3)(FIGs. 1, 5; ¶0073) according to the second control signal(CS2)(FIG. 5; ¶¶0045, 0068, 0073 – DL6 is coupling connected to the left one of pair of lines directly connected to OC3 via CS2).
As to claim 19, Kim and Kim II teach the display apparatus of claim 16, as applied above.
Kim further discloses wherein the display (FIGs. 1-2: DSP; ¶¶0030-0031) further comprises second voltage transfer lines(any one of each PXL’s horizontal line shown as: a horizontal line directly below ELVDD, a horizontal line directly above Vint, a horizontal line directly above ELVSS or the horizontal lines shown as SLN-1)(FIGs. 1-2, 4-5; ¶¶0034, 0049) extending in the row direction (FIGs. 1-2, 4-5: any one of each PXL’s horizontal line shown as: a horizontal line directly below ELVDD, a horizontal line directly above Vint, a horizontal line directly above ELVSS or the horizontal lines shown as SLN-1; ¶¶0034, 0049), and the first voltage transfer lines(for each PXL: a vertical line providing ELVDD)(FIG. 4; ¶0034) are connected to the second voltage transfer lines(any one of each PXL’s horizontal line shown as: a horizontal line directly below ELVDD, a horizontal line directly above Vint, a horizontal line directly above ELVSS or the horizontal lines shown as SLN-1)(FIGs. 1-2, 4-5; ¶¶0034, 0049 – second voltage transfer lines {FIGs. 1-2, 4-5: any one of each PXL’s horizontal line shown as: a horizontal line directly below ELVDD, a horizontal line directly above Vint, a horizontal line directly above ELVSS or the horizontal lines shown as SLN-1} is either directly or coupling connected to the first voltage transfer lines {FIG. 4: for each PXL: a vertical line providing ELVDD}).
7. Claims 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2016/0019842 A1 to Kim in view of U.S. Patent Pub. No. 2019/0080651 A1 to Kim et al. (“Kim II”) as applied to claim 16 above, in view of U.S. Patent Pub. No. 2017/0221979 A1 to Chae.
As to claim 25, Kim and Kim II teach the display apparatus of claim 16 as applied above.
Kim and Kim II teach do not expressly disclose an electronic device comprising the display apparatus of claim 16.
Chae discloses an electronic device (¶0275) comprising a display apparatus (FIGs. 1-2; ¶¶0083, 0275).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim and Kim II with Chae to provide a display apparatus that can be conveniently moved to different locations.
As to claim 26, Kim, Kim II and Chae teach the electronic device of claim 25, as applied above.
Chae further discloses wherein, the electronic device (¶0275) is a mobile phone (¶0275), a smartphone (¶0275), a tablet personal computer (¶0275), a mobile communication terminal (¶0275), an electronic notebook (¶0275), an electronic book (¶0275), a portable multimedia player, a navigation, an ultra-mobile PC, a television, a laptop (¶0275), a monitor, a billboard, an Internet-of-Things device, a smart watch, a watch phone, a glasses-type display, a head-mounted display, a center information display disposed on a center fascia or dashboard of a vehicle, a room mirror display, or a display disposed on a rear surface of a front seat of the vehicle.
The motivation to combine the additional teachings of claim 26 is for the same reasoning set forth above for claim 25.
Allowed Claims/Allowable Subject Matter
8. Claims 1-15 and 21-24 are allowed. Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
9. The following is examiner’s statement of reasons for allowance: the claimed invention is directed to:
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Independent claim 1 identifies the distinct features: “for every three sequential sub-pixel columns(FIG. 6: columns 1-3 and 4-6 of pixels PC), sub-pixel circuits in one sub-pixel circuit column(FIG. 6: columns 2 and 5 of pixels PC) among the three sequential sub-pixel circuit columns(FIG. 6: columns 1-3 and 4-6 of pixels PC) have a flipped shape(FIG. 6: columns 2 and 5 of pixels PC) and sub-pixel circuits in other sub-pixel circuit columns(FIG. 6: columns 1, 3-4 and 6 of pixels PC) among the three sequential sub-pixel circuit columns(FIG. 6: columns 1-3 and 4-6 of pixels PC) have a non-flipped shape(FIG. 6: columns 1-3 and 4-6 of pixels PC)”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2020/0043406 A1 to Cha et al. (“Cha”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 1, Cha discloses a display apparatus (FIG. 1: 100; ¶0043) comprising:
a display(100)(FIG. 1; ¶0043) comprising sub-pixel circuits(SPX)(FIGs. 1, 3, 5; ¶¶0057, 0108-0112) arranged in a row direction and a column direction (FIGs. 3, 5: SPX; ¶¶0108-0112) and data lines(D1-D4, etc.)(FIGs. 1-3, 5; ¶¶0078, 0116 – since other plurality of switch circuits SC exists besides the one shown in FIG. 2 {¶0078}, there must be at least another four more data lines for each of these SCs) connected to corresponding sub-pixel circuits(SPX)(FIGs. 1, 3, 5: 140; ¶¶0057, 0108-0112);
a data driving circuit(120)(FIG. 1; ¶0052) that outputs data signals through output lines(B1-BM)(FIGs. 1-3; ¶¶0052-0054);
a data distributor(130, SC)(FIGs. 1-3; ¶¶0056, 0076) selectively connecting each of the output lines(B1-BM)(FIGs. 1-3; ¶¶0052-0054) to one(D1 or D3 of DG1; D2 or D4 of DG2)(FIGs. 2-3; ¶0056) of a corresponding pair of data lines(DG1/D1&D3, DG2/D2&D4)(FIGs. 2-3; ¶0056) among the data lines(D1-D4, etc.)(FIGs. 1-3, 5; ¶¶0078, 0116) according to a first control signal(CLa)(FIGs. 1-4: SC; ¶¶0082-0084) and a second control signal(CLb)(FIGs. 1-4: SC; ¶¶0082-0084); and
a control circuit(110)(FIG. 1; ¶0044) that alternately outputs the first control signal(CLa)(FIGs. 1-4: SC; ¶¶0048, 0082-0084) and the second control signal(CLb)(FIGs. 1-4: SC; ¶¶0048, 0082-0084), wherein
the data lines(D1-D4, etc.)(FIGs. 1-3, 5; ¶¶0078, 0116) comprise a first data line(D1)(FIGs. 2-3, 5; ¶0065), a second data line(D3)(FIGs. 2-3, 5; ¶0065), a third data line(D2)(FIGs. 2-3, 5; ¶0065), and a fourth data line(D4)(FIGs. 2-3, 5; ¶0065),
the first data line(D1)(FIGs. 2-3, 5; ¶0065) and the second data line(D3)(FIGs. 2-3, 5; ¶0065) are neighboring each other (FIGs. 2-3, 5: D1, D3; ¶0065) and each receives a corresponding data signal (FIGs. 2-3, 5: D1, D3; ¶¶0065, 0084), according to different ones of the first control signal(CLa)(FIGs. 1-4: SC, D1; ¶¶0048, 0082-0084) and the second control signal(CLb)(FIGs. 1-4: SC, D3; ¶¶0048, 0082-0084),
the third data line(D2)(FIGs. 2-3, 5; ¶0065) and the fourth data line(D4)(FIGs. 2-3, 5; ¶0065) are neighboring each other (FIGs. 2-3, 5: D2, D4; ¶0065) and each receives a corresponding data signal (FIGs. 2-3, 5: D2, D4; ¶¶0065, 0084), according to a same one of the first control signal(CLa)(FIGs. 1-4: SC, D2; ¶¶0048, 0082-0084) and the second control signal(CLb)(FIGs. 1-4: SC, D4; ¶¶0048, 0082-0084),
the first data line(D1)(FIGs. 2-3, 5; ¶0065) and the second data line(D3)(FIGs. 2-3, 5; ¶0065) are spaced apart from each other by at least one sub-pixel circuit column(from far left the 2nd and 3rd column of SPX)(FIGs. 1, 3, 5: 140; ¶¶0057, 0108-0112),
two neighboring data lines (FIG. 3; ¶0065 – FIG. 3 depicts at different regions: D1 and D3 are neighbors; D1 and D2 are neighbors; D2 and D4 are neighbors; D3 and D4 are neighbors) among the first data line(D1)(FIGs. 2-3, 5; ¶0065), the second data line(D3)(FIGs. 2-3, 5; ¶0065), the third data line(D2)(FIGs. 2-3, 5; ¶0065), and the fourth data line(D4)(FIGs. 2-3, 5; ¶0065) are arranged to face each other (FIG. 3; ¶0065 – FIG. 3 depicts at different regions: D1 and D3 are neighbors and face each other; D1 and D2 are neighbors and face each other; D2 and D4 are neighbors and face each other; D3 and D4 are neighbors and face each other), and
for every three sub-pixel circuit columns(see below edited FIG. 3, FIG. 5: SPX; ¶¶0108-0112), sub-pixels in one sub-pixel circuit column among the three sub-pixel circuit columns have a flipped shape(see below edited FIG. 3, FIG. 5: SPX; ¶¶0108-0112 – as shown below for every three sub-pixel circuit columns one sub-pixel column has a flipped shape. To get around the current grounds of rejection applicant may amend claim 1 to include “for every three sequentially adjacent sub-pixel circuit columns, sub-pixels in only one sub-pixel circuit column among the three sequentially adjacent sub-pixel columns have a flipped shape” or “for every three sequentially adjacent sub-pixel circuit columns, sub-pixels in one sub-pixel circuit column among the three sequentially adjacent sub-pixel columns have a flipped shape and sub-pixels two sub-pixel circuit columns among the three sequentially adjacent sub-pixel columns have a non-flipped shape”).
Cha does not disclose the above underlined limitations.
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Independent claim 11 identifies the distinct features: “one of the first voltage transfer lines(FIG. 11A: VLv) is disposed between the third data line(FIG. 11A: DL3) and the fourth data line(FIG. 11A: DL43)”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2016/0019842 A1 to Ki in view of U.S. Patent Pub. No. 2019/0080651 A1 to Kim et al. (“Kim II”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 11, Kim discloses a display apparatus (FIG. 1; ¶0030) comprising:
a display (FIGs. 1-2: DSP; ¶¶0030-0031) comprising sub-pixel circuits(R, G, B)(FIGs. 2, 5: PGO-PGE; ¶¶0031, 0033) arranged in a row direction and a column direction (FIGs. 2, 5: PGO-PGE, R, G, B; ¶¶0031, 0033), data lines(DL1-DLj)(FIGs. 1-2; ¶0031) connected to corresponding sub-pixel circuits(R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047), and first voltage transfer lines(for each PXL: a vertical line providing ELVDD)(FIG. 4; ¶0034) extending in the column direction (FIG. 4: for each PXL an ELVDD line; ¶0034);
a data driving circuit(DD)(FIGs. 1, 5; ¶0031) that outputs a data signal through output lines(OC1-OC6 and/or pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073);
a data distributor(D-MUX)(FIGs 1, 5; ¶0075) selectively connecting each of the output lines(OC1-OC6 and/or pairs of lines directly connected to each of OC1-OC6)(FIGs. 1, 5; ¶0073) to one of(one of: DL1/DL4, DL2/DL5, DL3/DL6, DL7/DL10, D8/D11, D9/D12)(FIGs. 1-2, 5; ¶0077) a corresponding pair of data lines(DL1/DL4, DL2/DL5, DL3/DL6, DL7/DL10, D8/D11, D9/D12)(FIGs. 1-2, 5; ¶0077) among the data lines(DL1-DLj)(FIGs. 1-2, 5; ¶0031) according to a first control signal(CS1)(FIG. 5; ¶0068) and a second control signal(CS2)(FIG. 5; ¶0068); and
a control circuit(D-MUX, CL1)(FIG. 5; ¶0068) that alternately outputs the first control signal(CS1)(FIG. 5; ¶0068) and the second control signal(CS2)(FIG. 5; ¶0068), wherein the data lines(DL1-DLj)(FIGs. 1-2, 5; ¶0031) comprise first groups(DL1-DL3, DL7-DL9)(FIGs. 1-2, 5; ¶0031) and second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2, 5; ¶0031),
each of the first groups(DL1-DL3, DL7-DL9)(FIGs. 1-2, 5; ¶0031) comprise a first data line(DL1, DL7)(FIGs. 1-2, 5; ¶0031), a second data line(DL2, DL8)(FIGs. 1-2, 5; ¶0031), and a third data line(DL3, DL9)(FIGs. 1-2, 5; ¶0031) that are sequentially arranged in the row direction (FIGs. 1-2, 5: DL1-DL3, DL7-DL9; ¶0031) and that receive data signals according to the first control signal(CS1)(FIG. 5; ¶¶0045, 0068, 0073),
each of the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2, 5; ¶0031) comprise a fourth data line(DL4, DL10)(FIGs. 1-2, 5; ¶0031), a fifth data line(DL5, DL11)(FIGs. 1-2, 5; ¶0031), and a sixth data line(DL6, DL12)(FIGs. 1-2, 5; ¶0031) that are sequentially arranged in the row direction (FIGs. 1-2, 5: DL4-DL6, DL10-DL12; ¶0031) and that receive data signals according to the second control signal(CS2)(FIG. 5; ¶¶0045, 0068, 0073),
the first groups(DL1-DL3, DL7-DL9)(FIGs. 1-2, 5; ¶0031) and the second groups(DL4-DL6, DL10-DL12)(FIGs. 1-2, 5; ¶0031) are alternately arranged in the row direction (FIGs. 1-2, 5: DL1-DL3, DL4-DL6, DL7-DL9, DL10-DL12; ¶0031),
one of the first voltage transfer lines(for each PXL: a vertical line providing ELVDD)(FIG. 4; ¶0034) is disposed between the third data line(DL3, DL9)(FIGs. 1-2, 5; ¶0031) and the fourth data line(DL4, DL10)(FIGs. 1-2, 5; ¶0031 – as shown in FIG. 4: each pixel has an ELVDD line at its left side with its data line Vdata at its right side),
sub-pixel circuits(R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047) arranged in odd-numbered sub-pixel circuit columns(odd numbered ones of 1-12 columns of R, G, B)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047), and the third data line(DL3)(FIGs. 1-2, 5; ¶0031) and the fourth data line(DL4)(FIGs. 1-2, 5; ¶0031), the sub-pixels arranged in even-numbered sub-pixel circuit columns(even-numbered columns of R, G, B sub-pixel circuits)(FIGs. 2, 4, 5: PGO-PGE; ¶¶0031, 0033, 0035, 0047) have a non-flipped shape (FIGs. 2, 4, 5: even-numbered columns of R, G, B sub-pixel circuits, PGO-PGE; ¶¶0031, 0033, 0035, 0047).
Kim does not expressly disclose sub-pixel circuits arranged in odd-numbered sub-pixel circuit columns have a flipped shape, and the third data line and the fourth data line are arranged to face each other.
Kim II discloses pixel circuits arranged in odd-numbered pixel circuit columns have a flipped shape (FIG. 5; ¶¶0073, especially – “the dummy pixel PD in some embodiments may be omitted”, 0094, 0129 - odd-numbered pixels are flipped with respect to even-numbered pixels. Also, dummy pixels PD and dummy data lines D0 may be omitted), and the third data line(D3)(FIG. 5; ¶0045) and the fourth data line(D4)(FIG. 5; ¶0045) are arranged to face each other (FIG. 5: D3, D4; ¶0045).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim with Kim II to provide a display apparatus that is brighter by having a higher aspect ratio (i.e., Kim discloses spacing on either side of each data line in the display area which is modified by Kim II so that a space on sides of two data lines is shared).
Kim and Kim II teach sub-pixel circuits arranged in odd-numbered sub-pixel circuit columns have a flipped shape (Kim: FIGs. 2, 4, 5: PGO-PGE, odd numbered ones of 1-12 columns of R, G, B; ¶¶0031, 0033, 0035, 0047; Kim II: FIG. 5; ¶¶0073, 0094, 0129), and the third data line and the fourth data line are arranged to face each other (Kim: FIGs. 1-2, 5: DL3, DL4; ¶0031; Kim II: FIG. 5: D3, D4; ¶0045).
Kim and Kim II do not teach the above underlined limitations.
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Dependent claim 20 identifies the distinct features: “wherein six data lines(FIG. 12A: DL7-DL12) are disposed between two neighboring first voltage transfer lines(FIGs. 10, 12A: neighboring VLvs) from among the first voltage transfer lines(FIGs. 10, 12A: VLvs)”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2016/0019842 A1 to Kim and U.S. Patent Pub. No. 2019/0080651 A1 to Kim et al. (“Kim II”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 20, Kim and Kim II teach the display apparatus of claim 16, as applied above but does not disclose the above underlined limitations.
Other Relevant Prior Art
10. Other relevant prior art includes:
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U.S. Patent No. 5,805,128A to Kim et al. discloses pixels some of which are flipped and some of which are not flipped (FIG. 5: 6; col 3, ln 29-30).
Conclusion
11. THIS ACTION IS MADE NON-FINAL.
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/KIRK W HERMANN/Examiner, Art Unit 2623
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