DETAILED ACTION
This action is responsive to the application filed on 12/4/2024. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4, 6, 13 and 18 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 9 and 13 of U.S. Patent No. 12,175,287. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the above claims of the instant application is an obvious variant of a corresponding claim of U.S Patent No. 12,175,287.
However, claims 1 and 4 of USPAT No. 12,175,287 do not explicitly recite “a memory that stores data operands and instruction data” as claimed in the instant application, but the reference patent does disclose a memory storing data operands.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory of claims 1 and 4 of USPAT No. 12,175,287 to store both data operands and instruction data. It would have been obvious to one of ordinary skill in the art because it would allow a single memory to store both operand data and instruction data, opposed to using two separate memories, which would reduce manufacturing cost (e.g., less memory lowers cost) and produce a much simpler hardware design.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 1, lines 4 and 8 which state “instruction data …data of the instruction data” lacks clarity. The limitations lack clarity because it is unclear if “instruction data” are merely instructions or are some data or portion of instructions (e.g. an instruction operand, opcode bits, flag bit or any other portion bit or field of an instruction)? Based on paragraph [0030] of the specification the examiner believes “instruction data” are the instructions themselves and for purposes of examination will interpret instruction data to be the instructions.
The examiner suggests amending the limitations to state “…instructions…shifting the instructions…” as to improve clarity of the claim.
Claims 2, 4-5, 7-8, 13-14, 16-17, and 19-20 all include similar limitations as disclosed above with regards to claim 1 and are similarly rejected for the same reasons as claim 1 above.
Claims 2-12 and 14-20 are dependent upon one or more claims above and therefore are similarly rejected for including the deficiencies of one or more claims above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7, 11-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vorbach, PGPUB No. 2019/0377580, and further in view of Espig, PGPUB No. 2019/0042262.
In regards to claim 1, Vorbach discloses A system (Fig. 7 discloses ZZYX system) comprising: at least one processor ([0745]: wherein a ZZYX processor (element 0701) is disclosed) comprising: an array of computational elements ([0208, 0256 and 0746]: wherein an array of ALUs is disclosed (See Figs. 4 and 7))
a memory that stores data operands ([0257, 0265-0268 and 0747-0748]: wherein register memory and/or data cache stores data operands) and another memory that stores instruction data ([0217 and 0748]: wherein an instruction memory/cache is disclosed) to be processed by the array of computational elements ([0257 and 0262]: wherein the data operands and instructions are processed by the array of ALUs)
and, based on a defined temporal relationship, provides the data operands to respective computational elements of the array of computational elements ([0262, 0264, 0292-0294 and 0327]: wherein operand data is provided to array of ALUs based on a defined timing (for example providing data operands every clock cycle to a row of ALU’s)) and an instruction dispatch circuit that, based on shifting data of the instruction data along a first direction and a second direction, provides the instruction data to the array of computational elements, wherein the first direction and the second direction are relative to a direction of flow of data in the at least one processor. ([0217 and 0262-0264]: wherein instruction issue unit provides instructions to the array of ALUs, based on shifting instructions along a horizontal direction (see elements 0420-0421) to each ALU stage and along a vertical dataflow direction (see element 0423). Wherein each direction is relative to the direction of flow of data in the processor (See Figs. 3-4 and 7))
Vorbach does not disclose a memory that stores data operands and instruction data. While, Vorbach discloses two separate memories to store instructions and data operands, Vorbach does not disclose a single memory to store both data operands and instructions.
Espig discloses a memory that stores data operands and instruction data. ([0092]: wherein a single internal cache to store instructions and data is disclosed)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the instructions and data operands of Vorbach to be stored in a single memory as taught in Espig. It would have been obvious to one of ordinary skill in the art because it would have been seen as a simple substitution of one known element (using a single memory to store both instructions and data as taught in Espig) for another (using two separate memories to store instructions and data as taught in Vorbach) to yield predictable results (using a using a single memory to store both instructions and data) for the benefit using a unified memory storage which balances memory storage space between instructions and data to provide reduced manufacturing cost (e.g., less memory lowers cost) and produce a much simpler hardware design. (MPEP 2143, Example B).
Claim 13 is similarly rejected on the same basis as claim 1 above as claim 13 is the method claim corresponding to the system of claim 1 above.
In regards to claim 2, the combination of Vorbach and Espig disclose The system of claim 1 (see rejection of claim 1 above) wherein the at least one processor further comprises: a compiler that, based on the defined temporal relationship, generates a compiled program that indicates a timing at which the data operands and the instruction data are read from the memory and provided to the array of computational elements. (Vorbach [0262, 0280, 0327, 1183 and 1285]: wherein a compiler, based on a defined deterministic algorithm, generates a compiled program that indicates a timing at which data and instructions are provided to array)
Claim 14 is similarly rejected on the same basis as claim 2 above as claim 14 is the method claim corresponding to the system of claim 2 above. (Note: claim 14 states an additional limitation stating “prior to providing the data operands”. However, Vorbach discloses the limitation because a compiler generates a program at compile time, which would occur before data operands are provided at a latter runtime. Thus, Vorbach discloses the additional limitation)
In regards to claim 4, the combination of Vorbach and Espig disclose The system of claim 1 (see rejection of claim 1 above) wherein the respective computational elements of the array of computational elements are configured to process the data operands based upon the instruction data. (Vorbach [0257 and 0262-0266])
In regards to claim 5, the combination of Vorbach and Espig disclose The system of claim 1 (see rejection of claim 1 above) wherein the instruction dispatch circuit shifts the data of the instruction data along the first direction and the second direction in a staggered manner. (Vorbach [0217 and 0262-0264]: wherein instruction issue unit shifts instructions along a horizontal direction (see elements 0420-0421) to a first ALU stage and then in a next cycle shift along a vertical dataflow direction (see element 0423) to provide instructions to a next ALU stage and thus shifts instructions in a staggered (alternating) manner. (See Figs. 3-4 and 7))
Claim 17 is similarly rejected on the same basis as claim 5 above as claim 17 is the method claim corresponding to the system of claim 5 above.
In regards to claim 7, the combination of Vorbach and Espig disclose The system of claim 1 (see rejection of claim 1 above) wherein, during defined timing increments of the defined temporal relationship, the instruction data are moved only in the first direction. (Vorbach [0262-0264, 0292-0294 and 0327]: wherein each clock cycle (e.g. incrementing a clock cycle by one) an ALU row is issued instructions in a horizontal direction (See Figs. 3-4))
Claim 19 is similarly rejected on the same basis as claim 7 above as claim 19 is the method claim corresponding to the system of claim 7 above.
In regards to claim 11, the combination of Vorbach and Espig disclose The system of claim 1 (see rejection of claim 1 above) wherein the defined temporal relationship is during a same cycle. (Vorbach [0262, 0264, 0292-0294 and 0327]: wherein defined timing is during a single (e.g. same) clock cycle because operand data and instruction data is provided to one of the ALU stages/rows during a same clock cycle)
In regards to claim 12, the combination of Vorbach and Espig disclose The system of claim 1 (see rejection of claim 1 above) wherein the defined temporal relationship is separated by a defined delay. (Vorbach [0262, 0264, 0292-0294 and 0327]: wherein defined timing is separated by a defined clock cycle delay because operand data and instruction data is provided to a next or subsequent ALU stage/row in a next clock cycle using a pipeline delay)
In regards to claim 15, the combination of Vorbach and Espig disclose The method of claim 14 (see rejection of claim 14 above) wherein the generating comprises determining the timing based on a hardware configuration of the processor. (Vorbach [0262, 0280, 0327, 1183 and 1285]: wherein a compiler, based on a defined deterministic algorithm, generates a compiled program. Wherein the timing of the deterministic algorithm is based on a mapping and ordering of instructions to the ZZYX processor core configuration (e.g. hardware configuration))
In regards to claim 16, the combination of Vorbach and Espig disclose The method of claim 14 (see rejection of claim 14 above) wherein the generating comprises determining the timing based on a type of instruction in the instruction data. (Vorbach [0262, 0280, 0327, 1183 and 1285]: wherein a compiler, based on a defined deterministic algorithm, generates a compiled program. Wherein the timing of the deterministic algorithm is based on whether the instruction is a first row ALU type instruction to be mapped to a first row of ALUs, a second row ALU type instruction to be mapped to a second row of ALUs, etc. as indicated by instruction sequence set by compiler)
Claim(s) 3 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vorbach, Espig, and further in view of Ross, PGPUB No. 2017/0103313.
In regards to claim 3, the combination of Vorbach and Espig discloses The system of claim 1 (see rejection of claim 1 above). wherein the at least one processor further comprises: memory and the instruction dispatch circuit. (Vorbach: See Figs. 3-4 and 7: wherein memory and instruction issue unit are disclosed| Espig [0092]: wherein a single internal cache to store instructions and data is disclosed)
The combination of Vorbach and Espig does not disclose a control circuit that controls operations of memory and instruction dispatch.
Ross discloses a control circuit that controls operations ([0024 and Fig. 2]: wherein a sequencer controls various circuits and memories in a processor)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array processor of Vorbach and Espig to include a sequencer to control operations of an array processor as taught in Ross. It would have been obvious to one of ordinary skill in the art because using a sequencer to control operations of components of a processor can provide efficient synchronization of dataflow across processor components.
In regards to claim 9, the combination of Vorbach and Espig discloses The system of claim 1 (see rejection of claim 1 above).
The combination of Vorbach and Espig does not disclose wherein the data operands correspond to weights utilized to implement a model.
Ross discloses wherein the data operands correspond to weights utilized to implement a model ([0003, 0005, 0020, 0024 and 0030]: wherein weight operands are utilized to implement a neural network model)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array processor Vorbach and Espig to implement a neural network model using weights as operands as the array processor of Ross. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (using an array processor to implement a neural network model with weight inputs as taught in Ross) for another (using an array processor operating on generic operands) to obtain predictable results (using array processor to implement a neural network model with weight operands) (MPEP 2143, Example B). Additionally, it would provide added flexibility to the array processor of Vorbach.
In regards to claim 10, the combination of Vorbach and Espig discloses The system of claim 1 (see rejection of claim 1 above).
The combination of Vorbach and Espig does not disclose wherein the data operands correspond to activations utilized to implement a model.
Ross discloses wherein the data operands correspond to activations utilized to implement a model ([0003, 0005, 0020, 0024 and 0031]: wherein activation operands are utilized to implement a neural network model)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array processor Vorbach and Espig to implement a neural network model using activations as operands as the array processor of Ross. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (using an array processor to implement a neural network model with activation inputs as taught in Ross) for another (using an array processor operating on generic operands) to obtain predictable results (using array processor to implement a neural network model with activation operands) (MPEP 2143, Example B). Additionally, it would provide added flexibility to the array processor of Vorbach.
Allowable Subject Matter
Claims 6, 8, 18 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 6 filed on 12/4/2024. The prior art of record has not taught either individually or in combination and together with all other claimed features “The system of claim 1, wherein the first direction is parallel to a direction of a flow of data in the at least one processor, and wherein the second direction is perpendicular to the direction of the flow of data in the at least one processor.”
The closest prior art of record, Vorbach discloses shifting instructions in a first direction which is perpendicular to the direction of a flow of data in the processor and then in a second direction which is parallel to the direction of the flow of data of the processor; thus, Vorbach teaches the opposite configuration as disclosed in claim 6, and thus teaches away from the arrangement of claim 6.
Furthermore, while some limitations may be broadly disclosed in the other references cited, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claim 18 is similarly rejected on the same basis as claim 6 above.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 8 filed on 12/4/2024. The prior art of record has not taught either individually or in combination and together with all other claimed features “The system of claim 1, wherein, during defined timing increments of the defined temporal relationship, the instruction data are moved only in the second direction.”
The closest prior art of record, Vorbach discloses moving instructions in a first direction to a row of ALUs in a first stage during a clock cycle, then moving in a second direction in order to move instructions in the first direction to a next row of ALUs during a next clock cycle, thus Vorbach moves instructions in the first direction when moving instructions in the second direction. Therefore, Vorbach does not disclose “…during defined timing increments of the defined temporal relationship, the instruction data are moved only in the second direction” as claimed in claim 8 above.
Furthermore, while some limitations may be broadly disclosed in the other references cited, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claim 20 is similarly rejected on the same basis as claim 8 above.
Conclusion
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183
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