DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/22/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-35 of U.S. Patent No. 12/183,4047. Although the claims at issue are not identical, they are not patentably distinct from each other because the current invention claims similar limitations as the issued patent. In other words, the current application is broader than the issued patent. The current application recites similar limitations such as one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: determine whether an access command corresponds to a first type of memory cell within the one or more memory devices; and issue the access command to the one or more memory devices, wherein, based at least in part on the access command corresponding to the first type of memory cell, the access command comprises one or more bits indicating a setting for performing an access operation corresponding to the access command.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-3, 6-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2020/0293199 A1).
Regarding claim 2, Choi teaches a memory system, comprising:
one or more memory devices (Fig. 1, Memory units 200-1 to 200-n); and
processing circuitry (Fig. 1, controller 100) coupled with the one or more memory devices and configured to cause the memory system to:
determine whether an access command corresponds to a first type of memory cell within the one or more memory devices; and issue the access command to the one or more memory devices, wherein, based at least in part on the access command corresponding to the first type of memory cell, the access command comprises one or more bits indicating a setting for performing an access operation corresponding to the access command (Fig. 2, internal commands ICMD is generated on the basis of an access unit according to the types of memory, ¶0041. The internal command will have different instructions based on the number of cycles which will have different bits for indicating a setting for performing the access operation).
Regarding claim 3, Choi further teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: receive a first version of the access command that does not include the one or more bits indicating the setting for performing the access operation; and based at least in part on the access command corresponding to the first type of memory cell, create a second version of the access command that comprises the one or more bits indicating the setting for performing the access operation, wherein, to issue the access command to the one or more memory devices, the processing circuitry is configured to cause the memory system to issue the second version of the access command (Controller 100 will change the external command CMD to create an internal command ICMD, which changes one or more bits).
Regarding claim 6, Choi further teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: determine the setting for performing the access operation based at least in part on a partition that includes one or more memory cells subject to the access operation, wherein the access command comprises the one or more bits indicating the setting based at least in part on the one or more memory cells subject to the access operation being included in the partition (The internal command will have different instructions based on the number of cycles which will have different bits for indicating a setting for performing the access operation).
Regarding claim 7, Choi further teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: receive, prior to receiving the access command, a prefix command indicating whether the access command corresponds to the first type of memory cell, wherein the processing circuitry is configured to cause the memory system to determine that the access command corresponds to the first type of memory cell based at least in part on the prefix command (Fig. 2, The memory control will receive prefix command CMD and generate internal command ICMD based on the type of memory device).
Regarding claim 8, Choi further teaches the memory system of claim 2, wherein the setting for performing the access operation corresponds to one or more parameters for the access operation (¶0072).
Regarding claim 9, Choi further teaches the memory system of claim 8, wherein the one or more parameters for the access operation comprise a voltage for application during the access operation, a duration of application for the voltage during the access operation, a reference voltage for the access operation, a program verify command for the access operation, or any combination thereof (the internal command ICMD will indicate to the memory device whether the access operation is read or write operation which they require different parameters and voltages to perform the access operation).
Regarding claim 10, Choi further teaches the memory system of claim 2, wherein the setting for performing the access operation comprises one setting from among a group of settings, and wherein the group of settings comprises a first setting associated with faster write performance than at least one other setting from among the group of settings, a second setting associated with longer memory cell lifetime than at least one other setting from among the group of settings, a third setting associated with a manufacturing process for the one or more memory devices, or any combination thereof (the memory device can have different operation cycles, which the internal command ICMD will indicate which type of cycle the memory device will perform, which different cycles indicate different speed for the write operation, ¶0069 to ¶0072).
Regarding claim 11, Choi further teaches the memory system of claim 2, wherein the access command further comprises a first one or more bits indicating a column address, a second one or more bits indicating a page address, a third one or more bits indicating a plane setting, a fourth one or more bits indicating a block address, a fifth one or more bits indicating a logical address, or any combination thereof (¶0097).
Regarding claim 12, Choi further teaches the memory system of claim 2, wherein the access command comprises a read command or a write command or an erase command (read or program commands, see ¶0069-¶0075).
Allowable Subject Matter
Claims 13-21 would be allowable if the double patenting rejection above is overcame.
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the double patenting rejection is overcame.
The following is a statement of reasons for the indication of allowable subject matter:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
With regards to claim 4, the one or more bits correspond to one or more bit indices for the access command; and the one or more bit indices are configured to indicate the setting for performing the access operation when the access command corresponds to the first type of memory cell and to indicate at least a portion of an address for one or more memory cells when the access command corresponds to a second type of memory cell.
With regards to claim 5, wherein the processing circuitry is further configured to cause the memory system to: determine whether an additional access command corresponds to the first type of memory cell; and determine, based at least in part on the additional access command corresponding to a second type of memory cell, that an additional one or more bits within the additional access command indicate at least a portion of an address associated with the additional access command, the additional one or more bits corresponding to a same one or more bit indices as the one or more bits.
With regards to claim 13, determine, based at least in part on whether the access command corresponds to the first type of memory cell, whether one or more bits of the access command indicate a setting for performing an access operation corresponding to the access command or indicate at least a portion of an address associated with the access command; and perform the access operation in accordance with the setting based at least in part on determining that the access command corresponds to the first type of memory cell and that the one or more bits of the access command indicate the setting.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
Prosecution Insights