DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
This Office action is in response to the Preliminary Amendment dated 2/6/2025.
Claims 1-20 are cancelled.
Claims 21-40 are added.
Claims 21-40 are pending.
Claims 21, 32, and 40 are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/4/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Use of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function.
Absence of the word “means” (or “step for”) in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function.
Claim elements in this application that use the word “means” (or “step for”) are presumed to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Similarly, claim elements that do not use the word “means” (or “step for”) are presumed not to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
Claim limitations “means for outputting to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register” and “[means for outputting to the DRAM via the first interface:] a first command instructing the DRAM to write the register data from the programmable register into the core storage array” of independent claim 40 have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because they use a generic placeholder “means for” coupled with functional language “outputting to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register” and “[outputting to the DRAM via the first interface:] a first command instructing the DRAM to write the register data from the programmable register into the core storage array” without reciting sufficient structure to achieve the functions. Furthermore, the generic placeholder is not preceded by a structural modifier.
Since the claim limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, independent claim 40 has been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: command/address paths, buses, signal lines, data links (see paragraphs 0016, 0018, 0032, 0042, and 0056 of the specification of the instant application).
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitations treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim so that it will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 21, 32, and 40 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by USPGPUB 2002/0046331 (“Davis”).
As per claim 21, Davis substantially teaches a memory control component to control an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array (Davis, Fig. 6), the memory control component comprising:
an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array: (Davis, Abstract; Fig. 6, reference numerals 100 and 170; Fig. 7, reference numerals 170 and 780; and paragraphs 0005, 0066, and 0101-0103, where the memory device of Davis, which may be embodied as a Dynamic Random Access Memory (DRAM), comprises memory core 200 that includes a storage array (i.e., a core storage array) and write data operations unit 170, which may include buffers (i.e., programmable registers) for temporarily storing data to be written to memory core 200. Davis therefore substantially teaches an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array);
a first interface; and control circuitry to output to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register; and a first command instructing the DRAM to write the register data from the programmable register into the core storage array: (Davis, Abstract; Fig. 6, reference numerals 112, 114, 150, and 170; Fig. 7, reference numerals 170, 700, 705, 720, and 780; and paragraphs 0005, 0066, and 0101-0111, where the memory device of Davis may receive a write command, which necessarily includes data to be written, directed to the storage array of memory core 200. The write command is received by transfer, control, distribution, and sequencing (TCDS) block 705 (i.e., a first interface) via received control signals 700, and the data to be written is directed by TCDS 705 to be temporarily buffered to write data buffer 780 of write data operation unit 170. In other words, TCDS 705 outputs a register-write instruction and register data to be written to the register. When a signal to execute the write operation is received, TCDS 705 causes buffered data temporarily stored in write data buffer 780 to be stored to the storage array of memory core 200. Davis therefore substantially teaches a first interface; and control circuitry to output to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register; and a first command instructing the DRAM to write the register data from the programmable register into the core storage array).
As per claim 32, Davis substantially teaches a method of operation within a memory control component having a first interface coupled to an integrated-circuit dynamic random access memory (DRAM), the method comprising:
a memory control component having a first interface coupled to an integrated-circuit dynamic random access memory (DRAM): (Davis, Abstract; Fig. 6, reference numerals 100 and 170; Fig. 7, reference numerals 170 and 780; Fig. 7, reference numerals 700 and 705; and paragraphs 0005, 0066, and 0101-0111, where the memory device of Davis, which may be embodied as a Dynamic Random Access Memory (DRAM), comprises memory core 200 that includes a storage array (i.e., a core storage array) and write data operations unit 170, which may include buffers (i.e., programmable registers) for temporarily storing data to be written to memory core 200. A write command is received by transfer, control, distribution, and sequencing (TCDS) block 705 (i.e., a first interface) via received control signals 700, and the data to be written is directed by TCDS 705 to be temporarily buffered. Davis therefore substantially teaches a memory control component having a first interface coupled to an integrated-circuit dynamic random access memory (DRAM));
outputting a register-write instruction and register data to the DRAM via the first interface, the register-write instruction instructing the DRAM to store the register data within a programmable register of the DRAM; and outputting a first command to the DRAM via the first interface, the first command instructing the DRAM to write the register data from the programmable register into a core storage array of the DRAM: (Davis, Abstract; Fig. 6, reference numerals 112, 114, 150, and 170; Fig. 7, reference numerals 170, 700, 705, 720, and 780; and paragraphs 0005, 0066, and 0101-0111, where the memory device of Davis may receive a write command, which necessarily includes data to be written, directed to the storage array of memory core 200. The write command is received by transfer, control, distribution, and sequencing (TCDS) block 705 (i.e., a first interface) via received control signals 700, and the data to be written is directed by TCDS 705 to be temporarily buffered to write data buffer 780 of write data operation unit 170. In other words, TCDS 705 outputs a register-write instruction and register data to be written to the register. When a signal to execute the write operation is received, TCDS 705 causes buffered data temporarily stored in write data buffer 780 to be stored to the storage array of memory core 200. Davis therefore substantially teaches outputting a register-write instruction and register data to the DRAM via the first interface, the register-write instruction instructing the DRAM to store the register data within a programmable register of the DRAM; and outputting a first command to the DRAM via the first interface, the first command instructing the DRAM to write the register data from the programmable register into a core storage array of the DRAM).
As per claim 40, Davis substantially teaches a memory control component to control an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array (Davis, Fig. 6), the memory control component comprising:
an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array: (Davis, Abstract; Fig. 6, reference numerals 100 and 170; Fig. 7, reference numerals 170 and 780; and paragraphs 0005, 0066, and 0101-0103, where the memory device of Davis, which may be embodied as a Dynamic Random Access Memory (DRAM), comprises memory core 200 that includes a storage array (i.e., a core storage array) and write data operations unit 170, which may include buffers (i.e., programmable registers) for temporarily storing data to be written to memory core 200. Davis therefore substantially teaches an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array);
a first interface; and means for outputting to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register; and a first command instructing the DRAM to write the register data from the programmable register into the core storage array: (Davis, Abstract; Fig. 6, reference numerals 112, 114, 150, and 170; Fig. 7, reference numerals 170, 700, 705, 720, and 780; and paragraphs 0005, 0066, and 0101-0111, where the memory device of Davis may receive a write command, which necessarily includes data to be written, directed to the storage array of memory core 200. The write command is received by transfer, control, distribution, and sequencing (TCDS) block 705 (i.e., a first interface) via received control signals 700, and the data to be written is directed by TCDS 705 to be temporarily buffered to write data buffer 780 of write data operation unit 170. In other words, TCDS 705 outputs a register-write instruction and register data to be written to the register. When a signal to execute the write operation is received, TCDS 705 causes buffered data temporarily stored in write data buffer 780 to be stored to the storage array of memory core 200. Davis therefore substantially teaches a first interface; and means for outputting to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register; and a first command instructing the DRAM to write the register data from the programmable register into the core storage array).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21, 32, and 40 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11, and 20 of U.S. Patent No. 11,748,252 (“Sheffler”). The following tables, in which similarities between claims 21, 32, and 40 of the instant application and claims 1, 11, and 20 of Sheffler are highlighted in bold, and accompanying reasoning illustrate that claims 21, 32, and 40 of the instant application are not patentably distinct from claims 1, 11, and 40 of Sheffler:
Instant Application, Independent Claim 21
Sheffler, Independent Claim 1
21. A memory control component to control an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array, the memory control component comprising: a first interface; and control circuitry to output to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register; and a first command instructing the DRAM to write the register data from the programmable register into the core storage array.
1. A memory controller component to control a memory integrated-circuit (IC) having a programmable register and a memory core, the memory controller component comprising: a command/address interface; a data interface; and control circuitry to: output, to the memory IC, a data-write command via the command/address interface and write data via the data interface, the data-write command instructing the memory IC to write the write data to the memory core; output, via the command/address interface, a register-write instruction and corresponding data values to the memory IC, the register-write instruction instructing the memory IC to store the data values within the programmable register; and output a memory access command and an address value to the memory IC via the command/address interface, the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value.
Independent claim 1 of Sheffler does not appear to explicitly claim “a dynamic random access memory (DRAM)”; however, the Examiner notes that a DRAM is a particular type of memory integrated circuit. It would have been obvious to a person having ordinary skill in the art before the invention of the instant application was made to use a DRAM as a particular memory integrated circuit because a person having ordinary skill in the art would be motivated to increase system flexibility by implementing memory integrated circuits that use standardized and widely-adopted DRAM.
In addition, the Examiner notes that independent claim 1 of Sheffler claims “[a] memory controller,” while independent claim 21 of the instant application claims “[a] memory control component.” The Examiner further notes that a memory controller necessarily comprises a memory control component in order to control memory.
Finally, the Examiner notes that independent claim 1 of Sheffler claims “a memory core,” while independent claim 21 of the instant application claims “a core storage array.” The Examiner notes that “a memory core” by definition includes “a core storage array” to enable storing data within “a memory core.”
Instant Application, Independent Claim 32
Sheffler, Independent Claim 11
32. A method of operation within a memory control component having a first interface coupled to an integrated-circuit dynamic random access memory (DRAM), the method comprising: outputting a register-write instruction and register data to the DRAM via the first interface, the register-write instruction instructing the DRAM to store the register data within a programmable register of the DRAM; and outputting a first command to the DRAM via the first interface, the first command instructing the DRAM to write the register data from the programmable register into a core storage array of the DRAM.
11. A method of operation within a memory controller component for controlling a memory integrated-circuit (IC) having a programmable register and a memory core, the method comprising: outputting, to the memory IC, a data-write command via a command/address interface of the memory controller component and write data via a data interface of the memory controller component, the data-write command instructing the memory IC to write the write data to the memory core; outputting, via the command/address interface, a register-write instruction and corresponding data values to the memory IC, the register-write instruction instructing the memory IC to store the data values within the programmable register; and outputting a memory access command and an address value to the memory IC via the command/address interface, the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the address value.
Independent claim 11 of Sheffler does not appear to explicitly claim “a dynamic random access memory (DRAM)”; however, the Examiner notes that a DRAM is a particular type of memory integrated circuit. It would have been obvious to a person having ordinary skill in the art before the invention of the instant application was made to use a DRAM as a particular memory integrated circuit because a person having ordinary skill in the art would be motivated to increase system flexibility by implementing memory integrated circuits that use standardized and widely-adopted DRAM.
In addition, the Examiner notes that independent claim 11 of Sheffler claims “[a] memory controller,” while independent claim 32 of the instant application claims “[a] memory control component.” The Examiner further notes that a memory controller necessarily comprises a memory control component in order to control memory.
Finally, the Examiner notes that independent claim 11 of Sheffler claims “a memory core,” while independent claim 32 of the instant application claims “a core storage array.” The Examiner notes that “a memory core” by definition includes “a core storage array” to enable storing data within “a memory core.”
Instant Application, Independent Claim 40
Sheffler, Independent Claim 20
40. A memory control component to control an integrated-circuit dynamic random access memory (DRAM) having a programmable register and a core storage array, the memory control component comprising: a first interface; and means for outputting to the DRAM via the first interface: a register-write instruction and register data, the register-write instruction instructing the DRAM to store the register data within the programmable register; and a first command instructing the DRAM to write the register data from the programmable register into the core storage array.
20. A memory controller component to control a memory integrated-circuit (IC) component having a programmable register and a memory core, the memory controller component comprising: a data interface to output write data to the memory IC and receive read data from the memory IC; and a command/address interface to output, to the memory IC: a memory write command and a first address value, the memory write command instructing the memory IC to write the write data to the memory core at locations indicated by the first address value; a register-write instruction and corresponding data values, the register-write instruction instructing the memory IC to store the data values within the programmable register; and a memory access command and a second address value, the memory access command instructing the memory IC to write the data values, sourced from the programmable register, to the memory core at locations indicated by the second address value.
Independent claim 11 of Sheffler does not appear to explicitly claim “a dynamic random access memory (DRAM)”; however, the Examiner notes that a DRAM is a particular type of memory integrated circuit. It would have been obvious to a person having ordinary skill in the art before the invention of the instant application was made to use a DRAM as a particular memory integrated circuit because a person having ordinary skill in the art would be motivated to increase system flexibility by implementing memory integrated circuits that use standardized and widely-adopted DRAM.
The Examiner notes that independent claim 20 of Sheffler claims both “a data interface” and “a command/address interface,” which correspond to the claims “means for outputting …” of independent claim 40 of the instant application.
In addition, the Examiner notes that independent claim 11 of Sheffler claims “[a] memory controller,” while independent claim 32 of the instant application claims “[a] memory control component.” The Examiner further notes that a memory controller necessarily comprises a memory control component in order to control memory.
Finally, the Examiner notes that independent claim 11 of Sheffler claims “a memory core,” while independent claim 32 of the instant application claims “a core storage array.” The Examiner notes that “a memory core” by definition includes “a core storage array” to enable storing data within “a memory core.”
Allowable Subject Matter
Claims 22-31 and 33-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Non-patent literature "Intelligent RAM (IRAM): chips that remember and compute”: teaches including a cache and processor in DRAM modules for data transfer and computation operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C Chappell whose telephone number is (571)272-5003. The examiner can normally be reached on 10:00 AM - 6:00 PM, Eastern.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at a (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel C. Chappell/Primary Examiner, Art Unit 2135
Daniel C. Chappell
Primary Examiner
Art Unit 2135