DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 to 5, 7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuji (2021/0296275) in view of Chang et al (2023/395574).
The Tsuji reference teaches a method of manufacturing a semiconductor device, note, entire reference. The method comprising forming a memory stack, memory cells arranged three-dimensionally on a cell wafer, substrate 10 of memory cell array wafer para 0027 and fig. 1. The cell wafer has a first crystal orientation and comprises a first silicon single crystal wafer note claim 5. There is a first upper surface and a first notch fig. 4a. The notch extending from an outer circumference of the cell wafer toward a central region of the cell wafer. On a second wafer forming a peripheral circuit stack or control circuit on a peripheral circuit wafer (substrate 20 of control circuit wafer; par. [0027] and fig. 1). The peripheral circuit wafer (20) comprises a second silicon single crystal wafer (see claim 5) and has a second crystal orientation different from the first crystal orientation (see claim 3). Then bonding the cell wafer (10) to the peripheral circuit wafer (20) such that the memory stack and the peripheral circuit stack contact one another para. 0028 and fig. 5. The first crystal orientation is defined by a first surface orientation and a first notch direction, crystal orientation is expressed as the first surface orientation and wherein the first crystal orientation comprises {111}. The sole difference between the instant claim and the prior art is the notch and wafer orientations. However, the Chang et al reference teaches bonding two substrates with devices on them together, where the combination of two different wafers (10 and 20) and respective orientations, in each case single crystalline silicon wafer types (100), (110) or (111) and respective orientations (100)<100>,(100)<110>, (110)<110>, (110)<111>, (110)<112>, (111)<110> and (111)<112> may be encompassed as long as those are pairwise different from each other (see pars. [0035]-[0039] and [0051]-[0055]). It would have been obvious to one of ordinary skill in the art before the filing date of the instant invention to modify the Tsuji process by the teachings of the Chang et al reference to use different orientations of the wafer and notch pairings in order to reduce stress between the two bonded wafers and devices.
With regards to claim 3, the Tsuji reference teaches para. 0003 and fig. 1 the implementation of three-dimensional NAND memories. The details of gate electrodes, vertical channels and horizontal extension directions of bit-lines figs. 1 and 2. The parallel extension of bit lines with the notch direction follows from fig. 1 with fig. 2.
With regards to claim 4 , the Tsuji reference teaches the placement of the peripheral circuit is shown in fig. 1 and the corresponding orientation of the second notch direction of the second notch (29) (in alignment with the first notch (19)) is disclosed in fig. 5.
With regards to claim 5 the Tsuji reference teaches in Fig. 1 electrical connections of bit lines to the peripheral circuit stack via respective, direct-bonded pads.
With regards to claim 7 the Tsuji reference teaches that the cell wafer substrate may optionally be removed after the wafer-to-wafer bonding.
Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuji (2021/0296275) in view of Chang et al (2023/395574).
The Tsuji and Chang et al references are relied on for the same reasons supra, and differs from the instant claims in the initial thicknesses of the wafers. However, it would have been obvious to one of ordinary skill in the art before the filing date of the instant invention to determine through routine experimentation the optimum, operable wafer thicknesses in the combined references in order to have a wafer that can solidly support the deposited layers.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuji (2021/0296275) in view of Chang et al (2023/395574).
The Tsuji and Chang et al references are relied on for the same reasons supra, and differs from the instant claim in the addition of a common source plate on the upper surface of the memory stack. However, it would have been obvious to one of ordinary skill in the art before the filing date of the instant invention to determine through routine experimentation the optimum, operable addition of a common plate in the combined references in order to allow electrical contacts for input and output form the stacks.
Claim(s) 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuji (2021/0296275) in view of Chang et al (2023/395574).
The Tsuji and Chang et al references are relied on for the same reasons supra, and differs from the instant claims in the grinding of the wafers. However, it would have been obvious to one of ordinary skill in the art before the filing date of the instant invention to determine through routine experimentation the optimum, operable wafer thicknesses removal means in the combined references in order to not destroy the grown devices between the wafers.
Claims 11 to 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11 to 14 and 17 to 20 stand allowable over the art of record. The prior art does not teach the specific grown devices, gate electrode, channels and bit lines in combination with the two separate substrates and bonding the two together as is now claimed.
Examiner’s Remarks
The remaining references are merely cited of interest as showing the state of the art in bonding substrate with semiconductor already grown.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT M KUNEMUND whose telephone number is (571)272-1464. The examiner can normally be reached M-F 8:00 am to 4:30 pm.
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RMK
/ROBERT M KUNEMUND/Primary Examiner, Art Unit 1714
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