DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2,6, 7 and 8 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 11, 12 and 13 of copending Application No. 18/981,416 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because f. claim patentably indistinct inventions and the claimed invention and the reference application were commonly owned under 35 U.S.C. 102(b)(2)(C) or deemed to be commonly owned under 35 U.S.C. 102(c) not later than the effective filing date under 35 U.S.C. 100(i) of the claimed invention, for applications examined under the first inventor to file (FITF) provisions of the AIA ..
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application
Application No. 18/981,416
Claim 1:
Claim 1: A semiconductor test device for testing an electrical connection of a semiconductor,
comprising:
wherein the first part comprises a first membrane portion comprising a plurality of first
aperture patterns in a thickness direction, and a first holder portion comprising a hollow region
and being connected to an edge of the first membrane portion,
the first membrane portion comprises: a first metal thin film portion having a plurality of
the first aperture patterns; and a first insulating layer portion having an insulating material coated
on a surface of the first metal thin film portion, the second part comprises: a second membrane portion comprising a plurality of second
aperture patterns in a thickness direction;
the second membrane portion comprises: a second metal thin film portion having a
plurality of the second aperture patterns; and a second insulating layer portion having an
insulating material coated on a surface of the second metal thin film portion,
a first conductive thin film layer is formed on a side surface of each of the first aperture
patterns, the second aperture patterns.
Claim 1:
Claim 1: A semiconductor test device for testing an electrical connection of a semiconductor, comprising: a first membrane portion comprising a plurality of first aperture patterns in a thickness direction; a second membrane portion connected to the first membrane portion and comprising a plurality of second aperture patterns in a thickness direction; and a holder portion comprising a hollow region and being connected to an edge of the first membrane portion, wherein the first membrane portion comprises a first metal thin film portion having a plurality of the first aperture patterns; and a first insulating layer portion having an insulating material coated on a surface of the first metal thin film portion, the second membrane portion comprises a second metal thin film portion having a plurality of the second aperture patterns; and a second insulating layer portion having an insulating material coated on a surface of the second metal thin film portion, and a conductive thin film layer is formed on side surfacethe second aperture patterns.
Claim 2. The semiconductor test device of claim 1, wherein the first metal thin film portion comprises a 1-1st metal thin film portion and a 1-2nd metal thin film portion connected to an upper portion of the 1-1st metal thin film portion, and the second metal thin film portion comprises a 2-1st metal thin film portion and a 2-2nd metal thin film portion connected to a lower portion of the 2-1st metal thin film portion.
Claim 3. The semiconductor test device of claim 1, wherein the first metal thin film portion comprises a 1-1st metal thin film portion and a 1-2nd metal thin film portion connected to an upper portion of the 1-1st metal thin film portion and the second metal thin film portion comprises a 2-1st metal thin film portion and a 2-2nd metal thin film portion connected to a lower portion of the 2-1st metal thin film portion.
Claim 6. The semiconductor test device of contact with a plurality of micro bumps formed on a lower portion of a semiconductor memory.
Claim 11. The semiconductor test device of micro bumps formed on a lower portion of a semiconductor memory.
Claim 7. The semiconductor test device of claim 1, wherein the first metal thin film portion and the second metal thin film portion is made of at least one of Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy, nickel alloy or nickel.
Claim 12. The semiconductor test device of claim 1, wherein the first metal thin film portion and the second metal thin film portion are made of at least one of Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy, or nickel.
Claim 8. The semiconductor test device of claim 1, wherein the first conductive thin film layer is formed in a horizontal direction at a top of the side surface of each of the first aperture patterns
Claim 13. The semiconductor test device of claim 1, wherein the conductive thin film layer is further formed in a horizontal direction at a top of the side surfaces of each of the first aperture patterns
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 8, 12 and 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tago et al (US PUB 2014/0327463), hereinafter Tago.
(Figure 21 of Tago is provided below with annotations for the applicant’s convenience)
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With respect to claim 1, Tago discloses a semiconductor test device for testing an electrical connection of a semiconductor (See paragraph [0055] in view of the abstract of Tago), comprising: a first part (See [301] in figure 21 of Tago); and a second part interconnected to the first part (See [305] in figure 21 of Tago), wherein the first part comprises a first membrane portion (See [307] in figure 22 of Tago) comprising a plurality of first aperture patterns in a thickness direction (See the plurality of patterns providing openings for [307] in figure 22 of Tago), and a first holder portion (See [321] in figure 21 of Tago) comprising a hollow region (See the annotated region labeled [A] in figure 21 of Tago above) and being connected to an edge of the first membrane portion (See how [321] is connected to [307] in figure 21 of Tago), the first membrane portion comprises: a first metal thin film portion having a plurality of the first aperture patterns (See [43] in paragraph [0061] of Tago); and a first insulating layer portion having an insulating material coated on a surface of the first metal thin film portion (See [15] in paragraph [0061] of Tago), the second part comprises: a second membrane portion (See [309] in figure 21 of Tago) comprising a plurality of second aperture patterns in a thickness direction (See the plurality of aperture patterns [C] in figure 21 of Tago above); and a second holder portion comprising a hollow region and being connected to an edge of the second membrane portion (See [B] in figure 21 of Tago above), the second membrane portion comprises: a second metal thin film portion having a plurality of the second aperture patterns (See [329] in figure 21 of Tago); and a second insulating layer portion having an insulating material coated on a surface of the second metal thin film portion (See [325] in figure 21 of Tago), a first conductive thin film layer is formed on a side surface of each of the first aperture patterns (See [317] in figure 21 of Tago), and a second conductive thin film layer is formed on a side surface of each of the second aperture patterns (See [327] in figure 21 of Tago).
With respect to claim 7, Tago discloses the semiconductor test device of claim 1, wherein the first metal thin film portion and the second metal thin film portion is made of at least one of Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy, nickel alloy or nickel (See paragraph [0005] of Tago).
With respect to claim 8, Tago discloses the semiconductor test device of claim 1, wherein the first conductive thin film layer is formed in a horizontal direction at a top of the side surface of each of the first aperture patterns (See [317] in figure 21 of Tago), or is further formed in the horizontal direction at a bottom of the side surface of each of the first aperture patterns, and the second conductive thin film layer is formed in the horizontal direction at a top of the side surface of each of the second aperture patterns (See [327] in figure 21 of Tago), or is further formed in the horizontal direction at a bottom of the side surface of each of the second aperture patterns.
With respect to claim 12, Tago discloses a semiconductor test device for testing an electrical connection of a semiconductor (See paragraph [0055] in view of the abstract of Tago),
comprising: a membrane portion (See [307] in figure 22 of Tago) comprising a plurality of aperture patterns in a thickness direction (See the plurality of patterns providing openings for [307] in figure 22 of Tago); and a holder portion (See [321] in figure 21 of Tago) comprising a hollow region (See the annotated region labeled [A] in figure 21 of Tago above) and being connected to an edge of the membrane portion (See how [321] is connected to [307] in figure 21 of Tago), wherein the above membrane portion comprises a metal thin film portion having a plurality of the aperture patterns (See [43] in paragraph [0061] of Tago) and an insulating layer portion having an insulating material coated on a surface of the metal thin film portion (See [15] in paragraph [0061] of Tago), a conductive thin film layer is formed on a side surface of each of the aperture patterns (See [317] in figure 21 of Tago), the metal thin film portion comprises a first metal thin film portion (See [43] in paragraph [0061] of Tago) and a second metal thin film portion connected to an upper portion of the first metal thin film portion (See [325] in figure 21 of Tago), and the first metal film portion and the second metal film portion have different widths (See that [43] in figure 9 of Tago and [325] in figure 21 of Tago have different widths).
With respect to claim 13, Tago discloses the semiconductor test device of claim 12, wherein a width of the first aperture pattern of the first metal thin film portion is greater than that of the second aperture pattern of the second metal thin film portion (See the thickness of [307] in figure 21 of Tago is greater than the thickness of [43] in figure 9 of Tago at the apex regions of each triangular section).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tago as applied to claim 1 above, and further in view of Bartelink (US PAT 5,189,505).
With respect to claim 9, Tago discloses the semiconductor test device of claim 1, but fails to disclose wherein widths of the first aperture pattern and the second aperture pattern are in a range of 5 µm to 100 µm. However, Bartelink does disclose wherein widths of the first aperture pattern and the second aperture pattern are in a range of 5 µm to 100 µm (See Col. 3, lines 15-43 of Bartelink). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tago to include the feature disclosed by Bartelink because doing so maximizes spatial optimization.
With respect to claim 17, Tago discloses the semiconductor test device of claim 12, but fails to disclose wherein a width of the aperture patterns is in a range of 5 µm to 100 µm. However, Bartelink does disclose wherein a width of the aperture patterns is in a range of 5 µm to 100 µm (See Col. 3, lines 15-43 of Bartelink). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tago to include the feature disclosed by Bartelink because doing so maximizes spatial optimization.
Claim(s) 10, 11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tago as applied to claim 1 above, and further in view of Kanda et al. (US PUB 2007/0231936), hereinafter Kanda.
With respect to claim 10, Tago discloses the semiconductor test device of claim 1, but fails to disclose wherein the first holder portion is formed from a silicon wafer, the first metal thin film portion is formed by electroforming on the silicon wafer, and the first metal thin film portion comprises an Invar or Super Invar material. However, Kanda does disclose wherein the first holder portion is formed from a silicon wafer, the first metal thin film portion is formed by electroforming on the silicon wafer, and the first metal thin film portion comprises an Invar or Super Invar material (See paragraph [0190] of Kanda). Furthermore, it would have been obvious to one of ordinary skill in the art to modify the device disclosed by Tago to include the feature disclosed by Kanda because doing so enables high durability electrical contacts.
With respect to claim 11, the combination of Tago and Kanda discloses the semiconductor test device of claim 10, wherein a connection portion including Ni and Si, or a connection portion including Fe, Ni and Si, is interposed between the first holder portion and the first metal thin film portion (See paragraph [0190] of Kanda).
With respect to claim 18, Tago discloses the semiconductor test device of claim 12, but fails to disclose wherein the holder portion is formed from a silicon wafer, the metal thin film portion is formed by electroforming on the silicon wafer, and the metal thin film portion comprises an Invar or Super Invar material. However, Kanda does disclose wherein the holder portion is formed from a silicon wafer, the metal thin film portion is formed by electroforming on the silicon wafer, and the metal thin film portion comprises an Invar or Super Invar material (See paragraph [0190] of Kanda). Furthermore, it would have been obvious to one of ordinary skill in the art to modify the device disclosed by Tago to include the feature disclosed by Kanda because doing so enables high durability electrical contacts.
Allowable Subject Matter
Claims objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 3-5 depend from double patenting rejected base claim 2, in lieu of an art rejection, and are therefore objected to.
With respect to claim 14, the prior art of record neither shows nor suggests the combination of structural elements wherein a portion where there is a difference between the first aperture pattern of the first metal thin film portion and the second aperture pattern of the second metal thin film portion is provided as a cantilever portion protruding inward from the aperture pattern.
Claim 15 depends from objected to claim 14 and is therefore also objected to.
With respect to claim 16, the prior art of record neither shows nor suggests the combination of structural elements wherein the hollow region of the holder portion is provided as a space in which a semiconductor memory is accommodated, and the aperture patterns correspond, respectively, to a plurality of micro bumps formed on a lower portion of the semiconductor memory.
Claims 19 and 20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 19, the prior art of record neither shows nor suggests the method comprising the steps of: (a) forming a first trench portion on a first surface of a support and a second trench portion located below the first trench portion and having a narrower width than the first trench portion; (b) forming a metal thin film portion within the first trench portion and the second trench portion; (c) forming a holder portion by etching away the support on a second surface opposite the first surface, leaving only an edge portion of the support; (d) forming an insulating layer of insulating material on a surface of the metal thin film portion; and (e) forming a conductive thin film layer at least on a side surface of the aperture pattern.
Claim 20 depends from allowed claim 19 and is therefore also allowed.
Conclusion
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/TEMILADE S RHODES-VIVOUR/Examiner, Art Unit 2858
/GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 9/19/2026
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