Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed December 4, 2024.
Status of claims to be treated in this office action:
a. Independent: 1
b. Pending: 1-20
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4, 13-16, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3 and 19 include the phrase “arranged sequentially”, claim 4 contains the phrase “arranged interleaved”, and claims 13-16 contain both phrases. The phrase “arranged sequentially” is indefinite because the numbering or labeling of components such as bit lines, word lines, and sub-blocks is arbitrary. It would be clearer to use claim language to specify that a consecutive group of the components are all connected in common to another component. Refer to para. [0063] on p.15 of the Specification. The phrase “arranged interleaved” is also indefinite for the same reasons; while interleaved indicates an alternating pattern, the claim language does not provide clarity on what it means for the group of components to be interleaved. An example is provided in para. [0068] on p.16 of the Specification that clarifies that the interleaving of a group of one component is in relation to a group of another component. Examiner recommends amended these claims to provide clarity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US Pub. 20170033111 A1; “Yamazaki”) in view of Aoki et al. (US Pub. 20230200051 A1; “Aoki”).
Regarding independent claim 1, Yamazaki discloses a dynamic random access memory ([0517]: the semiconductor device in the above embodiment is used for a memory chip…a main memory (which can be replaced with a DRAM module, for example)) comprising:
a block comprising an array of memory cells (Fig. 2: memory circuit 20; [0223]);
wherein the block comprises planes (cell array 50 and sense amplifier circuit 60; [0223]) stacked along a first axis (Z; see annotated screenshot below),
wherein the block is divided into multiple sub-blocks (plurality of memory cells 51a and plurality of memory cells 51b; [0223]) arranged along the second axis (Y), wherein each of the sub-blocks contains one of the columns of the memory cells (memory cells in 51a are connected to wiring WLa, memory cells in 51b are connected to the wiring WLb);
the dynamic random access memory ([0517]) further comprising:
local bit lines each extending along the first axis in one of the sub-blocks (two wirings BLa and BLb);
global bit lines (wiring GBLa, wiring GBLb; [0225]),
sense amplifiers (sense amplifiers 61; [0223])
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Yamazaki does not explicitly disclose:
a block comprising a three-dimensional array of memory cells;
each of the planes comprising a two-dimensional array of the memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first axis and the second axis,
wherein each of the sub-blocks contains one of the columns of the memory cells of each of the planes;
local bit lines each extending along the first axis in one of the sub-blocks and connected to one memory cell in each of the planes;
global bit lines, wherein one or more of the global bit lines are connected to the local bit lines in each of the sub-blocks; and
sense amplifiers each connected to one of the global bit lines.
However, Aoki teaches:
a block (Fig. 2: LMCA; [0048]) comprising a three-dimensional array of memory cells (Fig. 3: memory cells MC; [0050]);
each of the planes comprising a two-dimensional array of the memory cells (MC) organized in rows extending along a second axis (Y-direction) perpendicular to the first axis (Z) and columns extending along a third axis (X. Examiner notes that the selection of the second and third axis may be interchangeable) perpendicular to the first axis and the second axis,
wherein each of the sub-blocks (Fig. 5: MCAC) contains one of the columns of the memory cells of each of the planes ([0056]: As shown in FIG. 5, the sub array column MCA.sub.C comprises: the plurality of memory layers ML0-ML3 arranged in the Z direction; and the plurality of global bit lines GBL provided below these memory layers ML0-ML3);
local bit lines (Fig. 5: 104(BL)) each extending along the first axis (Z) in one of the sub-blocks (MCAC) and connected to one memory cell (each combination of a transistor structure 110(TrC) and a capacitor structure 130(CpC)) in each of the planes (plurality of memory layers ML0-ML3);
global bit lines (global bit lines GBL; [0056]), wherein one or more of the global bit lines are connected to the local bit lines in each of the sub-blocks (one GBL is connected to the two BLs in the sub-block MCAC); and
sense amplifiers (Fig. 13: plurality of sense amplifier units SAU; [0096]) each connected to one of the global bit lines ([0101]: The plurality of sense amplifiers SA included in the sense amplifier unit SAU are each connected to the global bit lines GBL.sub.C, GBL.sub.T).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Aoki to
Yamazaki wherein a block comprising a three-dimensional array of memory cells; each of the planes comprising a two-dimensional array of the memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first axis and the second axis, wherein each of the sub-blocks contains one of the columns of the memory cells of each of the planes; local bit lines each extending along the first axis in one of the sub-blocks and connected to one memory cell in each of the planes; global bit lines, wherein one or more of the global bit lines are connected to the local bit lines in each of the sub-blocks; and sense amplifiers each connected to one of the global bit lines in order to provide a three-dimensional device with minimized area increase, partially due to the arrangement of contact electrodes (Aoki, [0138]-[0140]).
Regarding claim 2, Yamazaki and Aoki together disclose all the limitations of claim 1, and further through Aoki:
wherein each of the global bit lines (Fig. 5: GBL) extends along the third axis (Y), and each of the sub-blocks is associated with a first group of the global bit lines (GBL in Fig. 5; also see multiple GBL in Fig. 3), and each global bit line of the first group is connected to a second group of the local bit lines in the sub-block (e.g. the two bit lines 104(BL) depicted in the cross-section shown in Fig. 5).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Aoki to
modified Yamazaki wherein each of the global bit lines extends along the third axis, and each of the sub-blocks is associated with a first group of the global bit lines, and each global bit line of the first group is connected to a second group of the local bit lines in the sub-block in order to provide a three-dimensional device with minimized area increase, partially due to the arrangement of contact electrodes (Aoki, [0138]-[0140]).
Regarding claim 3, Yamazaki and Aoki together disclose all the limitations of claim 2, and further through Aoki:
wherein the second group of the local bit lines (the two bit lines 104(BL) depicted in the cross-section shown in Fig. 5) are arranged sequentially along the third axis (this pair of bit lines are aligned in the Y-direction).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Aoki to modfied Yamazaki wherein the second group of the local bit lines are arranged sequentially along the third axis in order to provide a three-dimensional device with minimized area increase, partially due to the arrangement of contact electrodes (Aoki, [0138]-[0140]).
Regarding claim 4, Yamazaki and Aoki together disclose all the limitations of claim 2, and further through Yamazaki:
wherein the second group of the local bit lines (bit lines BL depicted in Fig. 15A) are arranged interleaved along the third axis (the connections between bit lines and word lines are alternating along the X-axis. Examiner has given this limitation the broadest reasonable interpretation; see 112(b) rejection above).
Claims 5 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US Pub. 20170033111 A1) in view of Aoki (US Pub. 20230200051 A1) as applied to claim 1 above, and further in view of Kajigaya (US Pub. 20130070506 A1).
Regarding claim 5, Yamazaki and Aoki together disclose all the limitations of claim 1. Neither Yamazaki nor Aoki discloses:
wherein each of the global bit lines extends along the third axis and is connected to all of the local bit lines in one of the sub-blocks.
However, Kajigaya teaches:
wherein each of the global bit lines (Fig. 6: global bit line GBL; [0043]) extends along the third axis and is connected to all of the local bit lines in one of the sub-blocks (per Fig. 6, J local bit lines LBL(1) to LBL (J) are connected to global bit line GBL through the local sense amplifier LSA; [0043]: This structure enables the local sense amplifier LSA to sense and amplify the signal on a selected local bit line LBL through one input/output node Na and to output the signal to the global bit line GBL through the other input/output node Nb).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kajigaya to modfied Yamazaki wherein each of the global bit lines extends along the third axis and is connected to all of the local bit lines in one of the sub-blocks in order to decrease manufacturing time by forming capacitors on thin film transistor layer (Kajigaya, [0079]).
Regarding claim 17, Yamazaki and Aoki together disclose all the limitations of claim 1, and further through Aoki:
wherein each of the global bit lines (Fig. 5: GBL) extends along the second axis (Y), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Aoki to modfied Yamazaki wherein each of the global bit lines extends along the second axis in order to provide a three-dimensional device with minimized area increase, partially due to the arrangement of contact electrodes (Aoki, [0138]-[0140]).
Neither Yamazaki nor Aoki discloses:
each of the global bit lines is connected to one bit line in each of the sub-blocks of the block.
However, Kajigaya teaches:
each of the global bit lines is connected to one bit line in each of the sub-blocks of the block (through Fig. 6, para. [0043], and the same reasoning as applied to claim 5, the global bit line is connected physically through switches to each bit line, however, the global bit line may only be electrically connected to one selected local bit line at a time).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kajigaya to modfied Yamazaki wherein each of the global bit lines is connected to one bit line in each of the sub-blocks of the block in order to decrease manufacturing time by forming capacitors on thin film transistor layer (Kajigaya, [0079]).
Regarding claim 18, Yamazaki and Aoki together disclose all the limitations of claim 1, and further through Aoki:
wherein each of the global bit lines (Fig. 5: GBL) extends along the second axis (Y), sub-blocks (sub array column MCAC) of a group of the sub-blocks ([0048]: sub arrays MCAS) associated with the global bit line (GBL), and wherein different global bit lines are associated with different groups of the sub-blocks (Fig. 5 depicts a group of GBLs, so by extension, MCAS, comprising a group of MCAC, is associated with a larger group of GBLs).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Aoki to modified Yamazaki wherein each of the global bit lines extends along the second axis, and sub-blocks of a group of the sub-blocks associated with the global bit line, and wherein different global bit lines are associated with different groups of the sub-blocks in order to provide a three-dimensional device with minimized area increase, partially due to the arrangement of contact electrodes (Aoki, [0138]-[0140]).
Neither Yamazaki nor Aoki discloses:
each of the global bit lines is connected to one of the bit lines in each of the sub-blocks
However, Kajigaya teaches:
each of the global bit lines is connected to one of the bit lines in each of the sub-blocks (refer to claim 5 rejection using Fig. 6 and para. [0043])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kajigaya to modfied Yamazaki wherein each of the global bit lines is connected to one of the bit lines in each of the sub-blocks in order to decrease manufacturing time by forming capacitors on thin film transistor layer (Kajigaya, [0079]).
Regarding claim 19, Yamazaki, Aoki, and Kajigaya together disclose all the limitations of claim 18, and further through Aoki:
wherein each group of the sub-blocks (MCAS) are arranged sequentially along the second axis (in Fig. 4, MCAS are lined up along the Y-axis).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Aoki to modified Yamazaki wherein each group of the sub-blocks are arranged sequentially along the second axis in order to provide a three-dimensional device with minimized area increase, partially due to the arrangement of contact electrodes (Aoki, [0138]-[0140]).
Allowable Subject Matter
Claims 6-16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824 6/13/2026
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