DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 15-16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2023/0187202) in view of Zheng et al. “Area Selective Atomic Layer Deposition of TiN Using Trimethoxy(octadecyl)silane as a Passivation Layers.”
As to claim 15, Wang et al. further teaches a well structure having aluminum oxide on the bottom and side walls formed of silicon oxide. The silicon nitride is selectively applied to the side surfaces of silicon oxide (see Fig. 4b, 0009). Wang et al. teaches the use of ammonia plasma as a pre-treatment and further subsequent pulses of the ammonia plasma during the deposition of the silicon nitride (see 0005, 0015).
Wang et al. fails to teach the structure is formed of a first nitride on the bottom and sidewalls of a second nitride; the application of a self-assembled monolayer of an inhibitor on the first nitride and depositing a third nitride on the second nitride material as required by claim 15.
Wang et al. does teaches selectively the silicon nitride film depositing a film (see abstract) where the substrate having a first surface comprising titanium nitride, tantalum nitride, aluminum nitride, hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide (see 0020) and a second surface of a silicon nitride, silicon dioxide, germanium oxide, SiCO, SiC, SiON, or low-k materials (see 0019) is pretreated with ammonium plasma (see 0005, 0015) prior to depositing SiN on the second nitride surface (see 0019 and 0040-0042). Wang et al. teaches the deposition on the SiN, silicon dioxide, germanium oxide, SiCO, SiC, SiON, or low-k materials surface relative to the titanium nitride, tantalum nitride, aluminum nitride, hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide is 85 – 99% ( see 0062).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the process of Wang et al. to include the use of the bottom surface of the structure having a first nitride and a second nitride as the sidewalls and selectively applying a third nitride to the surface of the second nitride as claimed through routine experimentation depending upon the integrated circuit device being formed because Wang teaches titanium nitride, tantalum nitride or aluminum nitride as alternatives to aluminum oxide as well as silicon nitride as an alternative to silicon dioxide. It has been established that the mere substitution of one known element for another with same intended purpose provides predictable results.
Zheng et al. disclose how self-assembled monolayers (SAM) formed from silane based precursors can inhibit atomic layer deposition to achieve area-selective deposition. Zheng et al. shows that methyl-terminated silane precursor such as trimethoxy(octadecyl)silane (TMODS) forms densely packed and thermally stable SAM that suppresses precursor adsorption on non-growth surfaced during TiN atomic layer deposition. The TMDOS film has very high selective sensitivity (greater than about 0.99) up to 20 nanometers of deposited film in the growth area, showing that SAM surface passivation can strongly inhibit ALD nucleation in areas where its undesired (see abstract, Introduction, ASD Performance Evaluation of the Optimized TMODS Derived SAM films)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the process of Wang et al. to substitute the known silane SAM inhibitor as taught by Zheng et al. for the hydrogen inhibitor taught by Wang et al. One would have been motivated to do so since both are directed to reducing precursor nucleation on selected areas of a surface and Zheng et al. teaches an alternative inhibitor that does not require repeated cycles of the ammonia to achieve the desired thickness. Furthermore, it has been established that the mere substitution of one known element for another with the same intended use provides predictable results.
As to claim 16, TMDOS is an alkyl silane (taught by Zheng et al).
As to claim 18, Wang discloses the first material can be titanium nitride, tantalum nitride, or aluminum nitride (see 0041) and the second material can be silicon nitride, SiON , silicon dioxide (see 0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the process of Wang et al. to include the use of TiN and SiN from the disclosed list of materials through routine optimization depending on the integrated circuit device being formed because Wang explicitly teaches these materials as options in a disclosed finite list and teaches selective deposition between such surface classes.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2023/0187202) in view of Zheng et al. “Area Selective Atomic Layer Deposition of TiN Using Trimethoxy(octadecyl)silane as a Passivation Layers” as applied to claim 15, and in further view of Kaliappan et al. (US 2024/0297073).
The teachings of Wang et al. and Zheng et al. as applied to claim 15 are as stated above.
Wang et al. and Zheng et al. fail to teach pretreating with hydrogen plasma as required by claim 19 or removing the SAM layer via hydrogen plasma as required by claim 20.
Kaliappan et al. disclose treating a substrate with a blocking layer of silane SAM used for selective deposition of an ALD layer (0006, 0008. Kaliappan et al. teaches cleaning the surface prior to applying the self-assembled monolayer which helps improves SAM selectivity and helps control damage to the low-k materials (see 0059). Kaliappan teaches cleaning the surface with hydrogen plasma (see 0060).
It would have been further obvious to use the cleaning step taught by Kaliappan in the process of Wang et al. and Zheng et al. in order provide a clean surface. One would have been motivated to do so since both are directed to selective ALD depositing using SAM blocking layers where Kaliappan further teaches pre-cleaning improves SAM selectivity and prevent damage to the low K materials.
As to claim 20, Kaliappan further teaches removal of the blocking layer using hydrogen plasma (see 0060 and 0076).
Claim(s) 15-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dangerfield et al. (US 2023/0197438).
As to claim 15, Dangerfield et al. discloses a process of selectively applying a barrier layer (tantalum nitride) to a substrate that has a metal surface and a dielectric surface (see abstract). Dangerfield states the substrate can have a trench portion where the bottom surface is formed of a metal (including copper, cobalt, tungsten or titanium nitride – see 0034-0035 and 0040), a side well surface (dielectric layer see 0030) can be formed of (silicon oxides, silicon nitride, silicon carboxynitride, etc. – see 0030, 0055). A blocking layer (SAM – see 0063) is deposited on the metal surface, so the barrier layer is selectively grown on the dielectric surface (see 0055). Dangerfield et al. further states the silane used for the blocking dodecylsilanes (see 0045) or octylsilanes (see 0056). As shown in Fig. 3, the layer is selectively applied to the sidewall surface and not the metal surface – meeting passivation and inhibitor limitation.
Dangerfield et al. teaches a list of possible first and second surface materials. While nitride-to-nitride selectively is suggested, the specific pairing the surface having a first nitride and a second nitride, and depositing a third nitride on the second nitride is not explicitly taught by Dangerfield as required by claim 15.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the process of Dangerfield et al. to include the use of a surface having a first nitride and a second nitride and selectively applying a third nitride to the surface of the second nitride as claimed through routine experimentation depending upon the integrated circuit device being formed because Dangerfield teaches these materials as options in a disclosed finite list and teaches selective deposition between such surface classes.
As to claims 16-17, the inhibitor can be formed of an akylsilane (dodecylsilanes or octylsilanes (see 0045 and 0056).
As to claim 19, Dangerfield et al. teaches cleaning the surface (see 0048) with hydrogen plasma.
As to claim 20, Dangerfield et al. states the blocking material can be removed after forming the barrier material using hydrogen plasma (see 0048, 0065, Fig. 3 and 4).
Allowable Subject Matter
Claims 1 and 3-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the cited prior art fails to teach or suggest a substrate having a metal layer at the bottom of a feature, where a first nitride of TiN, WN, or TaN is applied directly to the metal and the feature has sidewalls extending from the bottom formed of a second nitride, silicon nitride, applying a SAM directly on the first nitride and applying a third nitride over the second nitride as required by claim 1.
Response to Arguments
Applicant's arguments filed 05/18/2026 in regards to the rejection of claims 15-16 , and 18 over Wang (US 2023/0187202) in view of Zheng have been fully considered but they are not persuasive. Applicant argues Zheng does not disclose using SAM to facilitate selective deposition of a third nitride on a second nitride located on trench sidewalls but not on a first nitride located on the trench bottom. The rejection does not rely on Zheng for teaching the trench geometry or arrangement of the first and second nitride materials. Rather, Zheng is relied upon solely for the known use of silane-derived self-assembled monolayer as an inhibitor for selective atomic layer deposition. Wang expressly teaches selective deposition of silicon nitride on silicon nitride while suppressing deposition on titanium nitride, tantalum nitride, aluminum nitride, and other materials. Therefore, the selection of these known materials for the bottom and sidewall portions o the semiconductor feature merely represents substitution of known materials for their known purpose of controlling selective deposition. The modification of Wang to employ the silane-derived self-assembled monolayer taught by Zheng merely substitutes one known surface passivation technique for another known surface passivation technique.
Applicant's arguments filed 05/18/2026 in regards to the rejection of claims 15-17 and 19-20 over Dangerfield et al. (US 2023/0197438) have been fully considered but they are not persuasive. Applicant argues that the office action improperly concludes that it would have been obvious to modify Dangerfield to include a surface having a first nitride and a second nitride and to selectively deposited a third nitride on the second nitride through routine experimentation. The rejection over Dangerfield teaches selective deposition using a surface blocking layer and that selection of known nitride materials as the respective deposition and non-deposition surface would have been within the level of ordinary skill in the art to achieve the known selective deposition especially since Dangerfield teaches a finite list of materials. Applicant further argues Dangerfield et al. fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a first nitride material deposited directly on a metal layer at the bottom of the at least one feature ) are not recited in the rejected claim(s) 15-20. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant has not made separate arguments addressing the limitations that are recited in claim 15, therefore the rejection of claims 15-17, 19, and 20 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Cachet I Proctor whose telephone number is (571)272-0691. The examiner can normally be reached Monday-Friday 7-3 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Cleveland can be reached at 571-272-1418. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CACHET I. PROCTOR/
Examiner
Art Unit 1712
/CACHET I PROCTOR/ Primary Examiner, Art Unit 1712
Prosecution Insights