DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is sent in response to Applicant’s Communication received 12/05/2024 for application number 18/969,684. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and claims.
Claims 1 – 30 are presented for examination.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner believes that the title of the invention is imprecise. A descriptive title indicative of the invention will help in proper indexing, classifying, searching, etc. See MPEP 606.01. However, the title of the invention should be limited to 500 characters.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show text labels for all the numbered blocks/boxes in FIG. 5-8, 10-11, 13-25 as described in the specification (for example there are no description in the drawings for parts 24, 28, 30, etc.). Text labels/names in the drawings are essential to understand what is being shown/described without further clarification from the specification. Without such text, one of ordinary skill in the art would not be able to identify what component is being shown in the drawings and would need additional analysis or evaluation to determine what component is being shown in the drawings. Simply assigning a part with a number is not considered a label because it does not identify what the part is. The definition of label is a brief description for the purposes of identification. If Applicant thinks the component is important enough to be assigned a number in the drawings, then it means the component is significant enough to be labeled so that one of ordinary skill in the art can understand what it is. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-23 of U.S. Patent No. 12,197,262. Although the claims at issue are not identical, they are not patentably distinct from each other because they are simple changes of a statutory category. Claim 1 of patent 12,197,262 include all the limitations of the instant claim 1 and therefore anticipates the instant claim. All features of instant dependent claims 2-29 are covered by claims 1-23 of patent 12,197,262 and are therefore rejected accordingly. The other independent claim 30 of the instant application is rejected under the same rationale and is covered by claim 1 of patent 12,197,262.
Claims 1-4, 6-7, 9-11, 15-16, 20-23, 25-27, and 29-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,591,283. Although the claims at issue are not identical, they are not patentably distinct from each other because they are simple changes of a statutory category. Claim 1 of patent 12,591,283 include all the limitations of the instant claim 1 and therefore anticipates the instant claim. All features of instant dependent claims 2-4, 6-7, 9-11, 15-16, 20-23, 25-27, and 29 are covered by claims 1-20 of patent 12,591,283 and are therefore rejected accordingly. The other independent claim 30 of the instant application is rejected under the same rationale and is covered by claims 1 of patent 12,591,283.
Comparisons of selected claims are shown in the following table.
Instant Application (18/969,684)
USPAT 12,197,262
USPAT 12,591,283
1. An apparatus comprising a dual-input power supply for providing power to a load comprising IT equipment that has a motherboard having load circuitry thereon, said power supply comprising a first power path, wherein said first power path connects electrical power to said load, wherein said power path comprises a first stage that comprises a power-factor correction circuit and a second stage that comprises a dc/dc converter, wherein said first stage is disposed either within a package that is off said motherboard or without a package and on said motherboard, and wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard.
1. An apparatus comprising a dual-input power supply for providing power to a load comprising IT equipment that has a motherboard having load circuitry thereon, said power supply comprising a first power path, wherein said first power path connects electrical power to said load, wherein said power path comprises a first stage that comprises a power-factor correction circuit and a second stage that comprises a dc/dc converter, wherein said first stage is disposed either within a package that is off said motherboard or without a package and on said motherboard, wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard, wherein said power supply comprises a second power path that connects a second input of said dual-input power supply to said load, wherein said second power path comprises a first stage comprising a power-factor correction circuit, wherein said second stage is common to both said first and second power paths, wherein said first stages of said power paths collectively define a pair of first stages that is disposed either within said package that is off said motherboard or without a package and on said motherboard, wherein each of said first stages comprises a winding and a capacitor that is parallel to said winding, and wherein said first stages are configured to cause said capacitors to cooperate to form a single hold-up capacitor that is shared by both said first and second power paths.
1. An apparatus comprising a power supply for providing power to a load comprising a server at a data center, said server comprising a motherboard having load circuitry thereon, said power supply comprising a power path that is connected to electrical power, wherein said power path connects to said load, wherein said power path comprises a first stage that comprises a power-factor correction circuit, wherein said power path further comprises a second stage that comprises a dc/dc converter, wherein said first stage of said power path is disposed either within a package that is off said motherboard or without a package and on said motherboard, and wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard; wherein said first stage comprises capacitors and transformers that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of voltages across each of said capacitors; and wherein said first stage is one of a pair of first stages.
2. The apparatus of claim 1, wherein said second stage is disposed on said motherboard without a package.
3. The apparatus of claim 1, wherein said pair of first stages and said second stage are both disposed on said motherboard along with said load circuitry and wherein said second stage is disposed on said motherboard with or without a package.
1… wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard
3. The apparatus of claim 1, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said pair of first stages and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage.
6. The apparatus of claim 1, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said pair of first stages and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage.
8. The apparatus of claim 1, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said first stage and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage.
4. The apparatus of claim 1, wherein said first stage comprises capacitors and transformers that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors.
5. The apparatus of claim 1, wherein said first stage comprises capacitors and transformers, that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors.
1… wherein said first stage comprises capacitors and transformers that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of voltages across each of said capacitors;
5. The apparatus of claim 1, wherein said power path is a first power-path and said dual-input power supply comprises a second power path, wherein said first power path connects a first input of said dual input power supply to said load and said second power path connects a second input of said dual input power supply to said load.
1. … wherein said power supply comprises a second power path that connects a second input of said dual-input power supply to said load,
6. The apparatus of claim 1, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said pair of first stages and said second stage, respectively, wherein said first heat shield is disposed to cover said pair of first stages and said second heat shield is disposed to cover said second stage.
7. The apparatus of claim 1, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said pair of first stages and said second stage, respectively, wherein said first heat shield is disposed to cover said pair of first stages and said second heat shield is disposed to cover said second stage.
9. The apparatus of claim 1, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said first stage and said second stage, respectively, wherein said first heat shield is disposed to cover said first stage and said second heat shield is disposed to cover said second stage.
7. The apparatus of claim 1, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said pair of first stages and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said pair of first stages and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage.
8. The apparatus of claim 1, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said pair of first stages and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said pair of first stages and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage.
10. The apparatus of claim 1, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said first stage and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said first stage and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage.
8. The apparatus of claim 1, wherein said power supply comprises a second power path that connects a second input of said dual-input power supply to said load, wherein said second power path comprises a first stage comprising a power-factor correction circuit, wherein said second stage is common to both said first and second power paths, wherein said first stages of said power paths collectively define a pair of first stages that is disposed either within said package that is off said motherboard or without a package and on said motherboard.
1. … a second power path that connects a second input of said dual-input power supply to said load, wherein said second power path comprises a first stage comprising a power-factor correction circuit, wherein said second stage is common to both said first and second power paths, wherein said first stages of said power paths collectively define a pair of first stages that is disposed either within said package that is off said motherboard or without a package and on said motherboard,
9. The apparatus of claim 8, wherein said pair of first stages is hot-swappable and said second stage is non-hot-swappable.
19. The apparatus of claim 1, wherein said pair of first stages is hot-swappable and said second stage is non-hot-swappable.
15. The apparatus of claim 1, wherein said first stage is hot-swappable and said second stage is non-hot-swappable.
10. The apparatus of claim 8, wherein said power supply is non-hot-swappable.
20. The apparatus of claim 1, wherein said power supply is non-hot-swappable.
16. The apparatus of claim 1, wherein said power supply is non-hot-swappable.
11. The apparatus of claim 8, wherein said pair of first stages and said second stage are hot swappable independently of each other.
21. The apparatus of claim 1, wherein said pair of first stages and said second stage are hot-swappable independently of each other.
17. The apparatus of claim 1, wherein said pair of first stages and said second stage are hot swappable independently of each other.
12. The apparatus of claim 8, wherein said first and second power paths share a common transformer.
10. The apparatus of claim 1, wherein said first and second power paths share a common transformer.
13. The apparatus of claim 8, wherein said first and second power paths share a common inductor.
11. The apparatus of claim 1, wherein said first and second power paths share a common inductor.
14. The apparatus of claim 8, wherein said first and second power paths share a common hold-up capacitor.
12. The apparatus of claim 1, wherein said first and second power paths share a common hold-up capacitor.
15. The apparatus of claim 8, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said pair of first stages and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said pair of first stages and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage.
8. The apparatus of claim 1, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said pair of first stages and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said pair of first stages and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage.
10. The apparatus of claim 1, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said first stage and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said first stage and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage
16. The apparatus of claim 8, wherein said power supply comprises a first package and a second package, wherein said pair of first stages is disposed within said first package, wherein said second stage is disposed within said second package, wherein said first package is insertable between said electrical power and said second package, and wherein said second package is insertable between said load and said first package, whereby said pair of first stages is removable from said power supply without removing said second stage, and whereby said second stage is removable from said power supply without removing said pair of first stages.
22. The apparatus of claim 1, wherein said power supply comprises a first package and a second package, wherein said pair of first stages is disposed within said first package, wherein said second stage is disposed within said second package, wherein said first package is insertable between said electrical power and said second package, and wherein said second package is insertable between said load and said first package, whereby said pair of first stages is removable from said power supply without removing said second stage, and whereby said second stage is removable from said power supply without removing said pair of first stages.
2. The apparatus of claim 1, wherein said power supply comprises a first package and a second package, wherein said first stage is disposed within said first package, wherein said second stage is disposed within said second package, wherein said first package is insertable between said electrical power and said second package, and wherein said second package is insertable between said load and said first package, whereby said first stage is removable from said power supply without removing said second stage, and whereby said second stage is removable from said power supply without removing said first stage.
17. The apparatus of claim 8, wherein said first stages of said first and second power paths each comprise a primary winding and wherein said primary windings are magnetically coupled to a secondary winding via a transformer.
14. The apparatus of claim 1, wherein said first stages of said first and second power paths each comprise a primary winding and wherein said primary windings are magnetically coupled to a secondary winding via a transformer.
18. The apparatus of claim 8, wherein said electrical power comprises power sources that work independently of each other, wherein each of said first stages of said first and second power paths comprises a transistor and a primary winding, wherein said transistor connects a corresponding one of said power sources to said primary winding, and wherein said power supply further comprises a controller that controls both of said transistors.
15. The apparatus of claim 1, wherein said electrical power comprises power sources that work independently of each other, wherein each of said first stages of said first and second power paths comprises a transistor and a primary winding, wherein said transistor connects a corresponding one of said power sources to said primary winding, and wherein said power supply further comprises a controller that controls both of said transistors.
19. The apparatus of claim 8, wherein said electrical power comprises power sources that work independently of each other and wherein said power supply is configured to draw power only from whichever one of said first and second power sources offers a higher voltage.
16. The apparatus of claim 1, wherein said electrical power comprises power sources that work independently of each other and wherein said power supply is configured to draw power only from whichever one of said first and second power sources offers a higher voltage.
20. The apparatus of claim 8, further comprising first and second shields disposed to surround said pair of first stages and said second stage, respectively, wherein said first and second shields have multiple apertures to promote air circulation.
17. The apparatus of claim 1, further comprising first and second shields disposed to surround said pair of first stages and said second stage, respectively, wherein said first and second shields have multiple apertures to promote air circulation.
13. The apparatus of claim 1, further comprising first and second shields disposed to surround said first stage and said second stage, respectively, wherein said first and second shields have multiple apertures to promote air circulation.
21. The apparatus of claim 8, further comprising first and second heat shields disposed to surround said pair of first stages and said second stage, respectively and first and second grounded electromagnetic interference shields disposed to suppress electromagnetic interference resulting from operation of said pair of first stages and said second stage, wherein said electromagnetic interference shields and said heat shields both comprise apertures, and wherein said apertures on said electromagnetic interference shields are smaller than said apertures on said heat shields.
18. The apparatus of claim 1, further comprising first and second heat shields disposed to surround said pair of first stages and said second stage, respectively and first and second grounded electromagnetic interference shields disposed to suppress electromagnetic interference resulting from operation of said pair of first stages and said second stage, wherein said electromagnetic interference shields and said heat shields both comprise apertures, and wherein said apertures on said electromagnetic interference shields are smaller than said apertures on said heat shields.
14. The apparatus of claim 1, further comprising first and second heat shields disposed to surround said first stage and said second stage, respectively and first and second grounded electromagnetic interference shields disposed to suppress electromagnetic interference resulting from operation of said first stage and said second stage, wherein said electromagnetic interference shields and said heat shields both comprise apertures, and wherein said apertures on said electromagnetic interference shields are smaller than said apertures on said heat shields.
22. The apparatus of claim 8, wherein said pair of first stages and said second stage are both disposed on said motherboard along with said load circuitry, wherein said second stage is disposed on said motherboard with or without a package.
3. The apparatus of claim 1, wherein said pair of first stages and said second stage are both disposed on said motherboard along with said load circuitry and wherein said second stage is disposed on said motherboard with or without a package.
1… wherein said first stage of said power path is disposed either within a package that is off said motherboard or without a package and on said motherboard, and wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard
23. The apparatus of claim 8, wherein said electrical power comprises dc power and wherein, when said power supply is connected to said dc power, said first stage is bypassed.
4. The apparatus of claim 1, wherein said electrical power comprises dc power and wherein, when said power supply is connected to said dc power, said first stage is bypassed.
7. The apparatus of claim 1, wherein said electrical power comprises dc power and wherein, when said power supply is connected to said dc power, said first stage is bypassed.
24. The apparatus of claim 8, wherein said electrical power comprise first and second power sources that operate independently of each other, wherein said second power path maintains a connection between said second power source and said IT equipment while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said IT equipment while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational, and wherein said first stages are isolated from each other.
9. The apparatus of claim 1, wherein said electrical power comprise first and second power sources that operate independently of each other, wherein said second power path maintains a connection between said second power source and said IT equipment while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said IT equipment while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational, and wherein said first stages are isolated from each other.
25. The apparatus of claim 8, wherein said first stage comprises capacitors and transformers, that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors.
5. The apparatus of claim 1, wherein said first stage comprises capacitors and transformers, that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors.
1… wherein said first stage comprises capacitors and transformers that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of voltages across each of said capacitors
26. The apparatus of claim 8, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said pair of first stages and said second stage, respectively, wherein said first heat shield is disposed to cover said pair of first stages and said second heat shield is disposed to cover said second stage.
7. The apparatus of claim 1, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said pair of first stages and said second stage, respectively, wherein said first heat shield is disposed to cover said pair of first stages and said second heat shield is disposed to cover said second stage.
9. The apparatus of claim 1, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said first stage and said second stage, respectively, wherein said first heat shield is disposed to cover said first stage and said second heat shield is disposed to cover said second stage.
27. The apparatus of claim 8, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said pair of first stages and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage.
6. The apparatus of claim 1, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said pair of first stages and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage.
8. The apparatus of claim 1, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said first stage and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage.
28. The apparatus of claim 8, wherein said apparatus is configured for providing continuity of power to said IT equipment, wherein said electrical power comprises first and second power sources that operate independently of each other, wherein said second power path maintains a connection between said second power source and said IT equipment while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said IT equipment while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational, and wherein said first stages of said first and second power paths are non-isolated from each other.
13. The apparatus of claim 1, wherein said apparatus is configured for providing continuity of power to said IT equipment, wherein said electrical power comprises first and second power sources that operate independently of each other, wherein said second power path maintains a connection between said second power source and said IT equipment while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said IT equipment while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational, and wherein said first stages of said first and second power paths are non-isolated from each other.
29. The apparatus of claim 8, wherein said power supply comprises a package that is insertable between said electrical power and said motherboard, wherein said pair of first stages is disposed within said package, and wherein said second stage is disposed or packaged alone on said motherboard along with said load circuitry.
2. The apparatus of claim 1, wherein said package is insertable between said electrical power and said motherboard, wherein said pair of first stages is disposed within said package, and wherein said second stage is disposed or packaged alone on said motherboard along with said load circuitry.
3. The apparatus of claim 1, wherein said power supply comprises a package that is insertable between said electrical power and said motherboard, wherein said first stage is disposed within said package, and wherein said second stage is disposed on said motherboard along with said load circuitry.
30. An apparatus comprising a power supply for providing power to a load comprising IT equipment that has a motherboard having load circuitry thereon, said power supply comprising a first power path, wherein said first power path connects electrical power to said load, wherein said power path comprises a first stage that comprises a power-factor correction circuit and a second stage that comprises a dc/dc converter, wherein said first stage is disposed either within a package that is off said motherboard or without a package and on said motherboard, and wherein said second stage is disposed or packaged alone on said motherboard.
1. An apparatus comprising a dual-input power supply for providing power to a load comprising IT equipment that has a motherboard having load circuitry thereon, said power supply comprising a first power path, wherein said first power path connects electrical power to said load, wherein said power path comprises a first stage that comprises a power-factor correction circuit and a second stage that comprises a dc/dc converter, wherein said first stage is disposed either within a package that is off said motherboard or without a package and on said motherboard, wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard, wherein said power supply comprises a second power path that connects a second input of said dual-input power supply to said load, wherein said second power path comprises a first stage comprising a power-factor correction circuit, wherein said second stage is common to both said first and second power paths, wherein said first stages of said power paths collectively define a pair of first stages that is disposed either within said package that is off said motherboard or without a package and on said motherboard, wherein each of said first stages comprises a winding and a capacitor that is parallel to said winding, and wherein said first stages are configured to cause said capacitors to cooperate to form a single hold-up capacitor that is shared by both said first and second power paths.
1. An apparatus comprising a power supply for providing power to a load comprising a server at a data center, said server comprising a motherboard having load circuitry thereon, said power supply comprising a power path that is connected to electrical power, wherein said power path connects to said load, wherein said power path comprises a first stage that comprises a power-factor correction circuit, wherein said power path further comprises a second stage that comprises a dc/dc converter, wherein said first stage of said power path is disposed either within a package that is off said motherboard or without a package and on said motherboard, and wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard; wherein said first stage comprises capacitors and transformers that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of voltages across each of said capacitors; and wherein said first stage is one of a pair of first stages.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 6-7, 9-11, 15-16, 20-22, and 26-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "said pair of first stages" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Furthermore, Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 3 would require the first and second stage to be located on the motherboard, as shown in FIG. 24 and paragraph [0145] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 6 would require the first and second stage to be located on the motherboard, as shown in FIG. 24 and FIG. 25, and paragraph [0145] and [0149] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 7 would require the first and second stage to be located on the motherboard, as shown in FIG. 25 and paragraph [0149] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first stage is off said motherboard and with a package and second stage is on said motherboard without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 9 would require the first stage to be off said motherboard to be hot-swappable, and second stage to be located on said motherboard to be non-hot-swappable. The only portion of Applicant’s PGPUB2025/0093930 that suggests a stage or component may be non-hot-swappable is paragraph [0146] which occurs when the stage is located on the motherboard. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Claim 10 recites “wherein said power supply is non-hot-swappable”, but it is unclear what it means for a power supply to be non-hot-swappable. Applicant’s PGPUB2025/0093930 appears to reference the stages being non-hot-swappable [0028], but there is no mention of the power supply itself being non-hot-swappable. There is no other mention of any element being non-hot-swappable in the specification, and thus it is unclear what this limitation means. For examination purposes, this limitation will be interpreted as the components on the power supply (e.g. first and second stage) are non-hot-swappable.
With such an interpretation, it would also require the structural cooperative relationships of the first stage and second stage are on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 10 with this interpretation would require both the first stage and second stage to be located on said motherboard to be non-hot-swappable. The only portion of Applicant’s PGPUB2025/0093930 that suggests a stage or component may be non-hot-swappable is paragraph [0146] which occurs when the stages are located on the motherboard. For examination purposes, this claim will also be interpreted to include the omitted structural connection.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first stage and second stage are off said motherboard and w a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 11 would require both the first stage and second stage to be located off said motherboard to be hot-swappable. Paragraph [0140] of Applicant’s PGPUB2025/0093930 indicates that first and second stage may be hot-swappable and independent of each other when they are not located on the motherboard. Paragraph [0146] indicates that being located on motherboard makes them non-hot-swappable. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 15 would require the first and second stage to be located on the motherboard, as shown in FIG. 25 and paragraph [0149] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first stage and second stage are off said motherboard and with a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 16 would require both the first stage and second stage to be located off said motherboard to be removable and insertable. Paragraph [0140] of Applicant’s PGPUB2025/0093930 indicates that first and second stage may be hot-swappable and independent of each other when they are not located on the motherboard. Paragraph [0146] indicates that being located on motherboard makes them non-hot-swappable. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 20 would require the first and second stage to be located on the motherboard, as shown in FIG. 24 and FIG. 25, and paragraph [0145] and [0149] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 21 would require the first and second stage to be located on the motherboard, as shown in FIG. 24 and FIG. 25 and paragraph [0145] and [0149] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Claim 22 recites “wherein said second stage is disposed on said motherboard with or without a package” but this is contradictory to claim 1 which claim 22 depends on. Claim 1 indicates that the second stage is either with a package and off said motherboard, or without a package and on said motherboard. The limitation in claim 22 that introduces the possibility of with a package on said motherboard directly contradicts the possible configurations stated in claim 1. Thus this limitation is unclear.
Claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 26 would require the first and second stage to be located on the motherboard, as shown in FIG. 24 and FIG. 25, and paragraph [0145] and [0149] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Similarly, Claim 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the first and second stages are to be on said motherboard and without a package. Independent claim 1 makes it ambiguous or broad on whether first and second stage are on or off the motherboard, but this limitation in claim 27 would require the first and second stage to be located on the motherboard, as shown in FIG. 24 and paragraph [0145] of Applicant’s PGPUB 2025/0093930. For examination purposes, this claim will be interpreted to include the omitted structural connection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamaki et al. (hereinafter as Yamaki) PGPUB 2011/0198924.
As per claim 1, Yamaki teaches an apparatus comprising a dual-input power supply [FIG. 3: (PSU 11 and PSU 14 (grouped together and collectively viewed as a dual-input power supply) both provide power to a load and are thus dual input power supply)] for providing power to a load comprising IT equipment that has a motherboard having load circuitry thereon [FIG. 3, 0003-0004, and 0030: (PSUs provide power to motherboard of a server (IT equipment), which provides power to its CPU (load circuitry))], said power supply comprising a first power path, wherein said first power path connects electrical power to said load [FIG. 3: (first power path goes through PSU 11 to motherboard to its loads)], wherein said power path comprises a first stage that comprises a power-factor correction circuit [FIG. 3 PFC circuit 16, 0035, and 0037-0038] and a second stage that comprises a dc/dc converter [FIG. 3 DC/DC converter 19 and 0043], wherein said first stage is disposed either within a package that is off said motherboard or without a package and on said motherboard [FIG. 3: (PFC circuit (first stage) is off motherboard) and 0067: (circuits such as the PFC circuit 16, may be an integrated circuit (within a package)], and wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard [FIG. 3: (DC/DC converter (second stage) is off the motherboard) and 0067: (circuits such as DC/DC converter 19, may be an integrated circuit (within a package)].
Claim 30 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-10, 12, 14-17, 20-22, 24, and 26-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogman PGPUB 2014/0001871, and further in view of Kinnard PGPUB 2013/0020872.
As per claim 1, Vogman teaches an apparatus comprising a dual-input power supply [FIG. 1 and FIG. 2: (power supply modules 12 (grouped together and viewed as a dual-input power supply))] for providing power to a load comprising IT equipment that has a motherboard having load circuitry thereon [FIG. 2 and 0018: (power provided to motherboard of a server) and 0019: (motherboard has host device and components)], said power supply comprising a first power path [FIG. 2: (power path from 12a to motherboard 38)], wherein said first power path connects electrical power to said load [FIG. 2: (power is delivered to motherboard from PSU 12a)], wherein said power path comprises a first stage that comprises a power-factor correction circuit [FIG. 2 power factor correction (PFC) stage 34)] and a second stage that comprises a dc/dc converter [FIG. 2 DC/DC converter 36], wherein said first stage is disposed off said motherboard [FIG. 2: (PFC is on the PSU and off motherboard)], and wherein said second stage is disposed off said motherboard [FIG. 2: (DC/DC converter is on the PSU and off motherboard)].
Vogman does not explicitly teach the complete limitation of wherein said first stage is disposed either within a package that is off said motherboard or without a package and on said motherboard, and wherein said second stage is disposed either within a package that is off said motherboard or without a package and on said motherboard. Specifically, Vogman indicates that the PFC and DC/DC converter are off motherboard, but does not explicitly indicate they are in a package. Although Vogman provides suggestions of using a package such as an integrated circuit [0030], and although it would be very obvious to one of ordinary skill in the art to simply encase the PFC or DC/DC converter in a packaged IC in the power module, Vogman nonetheless does not explicitly say the PFC or DC/DC converter are in a package.
Kinnard teaches power distribution circuitry for a server having multiple power supplies that each contain power factor correction and DC/DC conversion [FIG. 2 and FIG. 4]. Kinnard is thus similar to Vogman and are in the same field of endeavor because they both teach using multiple power inputs to power a computing load. Kinnard further teaches wherein said first stage is disposed within a package that is off said motherboard [FIG. 2 and FIG. 4: (DC outputs are provided to computing loads and the PFC is off the motherboard and on the power supply); and 0048: (circuit such as PFC may be an application specific integrated circuit (package)] and wherein said second stage is disposed within a package that is off said motherboard [FIG. 2 and FIG. 4: (DC outputs are provided to computing loads and the DC/DC converter is off the motherboard and on the power supply); and 0048: (circuit such as DC/DC converter may be an application specific integrated circuit (package)]. Kinnard teaches that circuitry may be in an integrated circuit, which is a package.
The combination of Vogman with Kinnard leads to Vogman’s PFC and DC/DC converter in the power supply each being a packaged integrated circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Kinnard’s teachings of placing PFC circuitry and DC/DC converter circuitry in a packaged IC chip in Vogman. One of ordinary skill in the art would have been motivated to put the PFC and DC/DC circuitry in an integrated circuit in Vogman because it allows for simple grouping/encapsulation of circuitry to better manage and replace them, thus allowing for easier replacement and repair.
As per claim 2, Vogman and Kinnard teach the apparatus of claim 1, wherein said second stage is disposed on said motherboard without a package [this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 3, Vogman and Kinnard teach the apparatus of claim 1, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said pair of first stages and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 5, Vogman and Kinnard teach the apparatus of claim 1, wherein said power path is a first power-path and said dual-input power supply comprises a second power path, wherein said first power path connects a first input of said dual input power supply to said load and said second power path connects a second input of said dual input power supply to said load [Vogman FIG. 2: (AC1 to load is first power path and AC2 to load is second power path)].
As per claim 6, Vogman and Kinnard teach the apparatus of claim 1, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said pair of first stages and said second stage, respectively, wherein said first heat shield is disposed to cover said pair of first stages and said second heat shield is disposed to cover said second stage [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 7, Vogman and Kinnard teach the apparatus of claim 1, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said pair of first stages and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said pair of first stages and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 8, Vogman and Kinnard teach the apparatus of claim 1, wherein said power supply comprises a second power path that connects a second input of said dual-input power supply to said load [Vogman FIG. 2 AC2 input to PSU module 2 to provide power to motherboard or Kinnard FIG. 4 and FIG. 5 path from source B to DC output], wherein said second power path comprises a first stage comprising a power-factor correction circuit [Vogman FIG. 2 PFC 34 or Kinnard FIG. 4 PFC in other PS], wherein said second stage is common to both said first and second power paths [Kinnard FIG. 5: (DC/DC converter (second stage) common to multiple PFC stages which each stage is a corresponding first and second path))], wherein said first stages of said power paths collectively define a pair of first stages that is disposed either within said package [Kinnard FIG. 2, FIG. 4, 0048: (PFC may be in an ASIC)] that is off said motherboard [Vogman FIG. 2: (PFC stages clearly off the motherboard)] or without a package and on said motherboard.
As per claim 9, Vogman and Kinnard teach the apparatus of claim 8, wherein said pair of first stages is hot-swappable and said second stage is non-hot-swappable [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 10, Vogman and Kinnard teach the apparatus of claim 8, wherein said power supply is non-hot-swappable [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 12, Vogman and Kinnard teach the apparatus of claim 8, wherein said first and second power paths share a common transformer [Kinnard FIG. 2: (first power path from main input and second power path from aux input share a T1 transformer)].
As per claim 14, Vogman and Kinnard teach the apparatus of claim 8, wherein said first and second power paths share a common hold-up capacitor [Kinnard FIG. 5: (common capacitor after PFC stages)].
As per claim 15, Vogman and Kinnard teach the apparatus of claim 8, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said pair of first stages and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said pair of first stages and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 16, Vogman and Kinnard teach the apparatus of claim 8, wherein said power supply comprises a first package and a second package, wherein said pair of first stages is disposed within said first package, wherein said second stage is disposed within said second package, wherein said first package is insertable between said electrical power and said second package, and wherein said second package is insertable between said load and said first package, whereby said pair of first stages is removable from said power supply without removing said second stage, and whereby said second stage is removable from said power supply without removing said pair of first stages [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 17, Vogman and Kinnard teach the apparatus of claim 8, wherein said first stages of said first and second power paths each comprise a primary winding and wherein said primary windings are magnetically coupled to a secondary winding via a transformer [Kinnard 0056 and FIG. 5: (PFC each have transformers)].
As per claim 20, Vogman and Kinnard teach the apparatus of claim 8, further comprising first and second shields disposed to surround said pair of first stages and said second stage, respectively, wherein said first and second shields have multiple apertures to promote air circulation [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 21, Vogman and Kinnard teach the apparatus of claim 8, further comprising first and second heat shields disposed to surround said pair of first stages and said second stage, respectively and first and second grounded electromagnetic interference shields disposed to suppress electromagnetic interference resulting from operation of said pair of first stages and said second stage, wherein said electromagnetic interference shields and said heat shields both comprise apertures, and wherein said apertures on said electromagnetic interference shields are smaller than said apertures on said heat shields [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 22, Vogman and Kinnard teach the apparatus of claim 8, wherein said pair of first stages and said second stage are both disposed on said motherboard along with said load circuitry, wherein said second stage is disposed on said motherboard with or without a package [this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 24, Vogman and Kinnard teach the apparatus of claim 8, wherein said electrical power comprise first and second power sources that operate independently of each other [Kinnard FIG. 2 (main input and aux input are independent power sources)], wherein said second power path maintains a connection between said second power source and said IT equipment while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said IT equipment while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational, and wherein said first stages are isolated from each other [Kinnard 0036: (power sources are isolated from each other and maintain configuration even if a power source fails; there is no disconnection performed based on failure and thus connections are maintained) and FIG. 4: (PFC from AC source is isolated from PFC of B input source (auxiliary)].
As per claim 26, Vogman and Kinnard teach the apparatus of claim 8, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said pair of first stages and said second stage, respectively, wherein said first heat shield is disposed to cover said pair of first stages and said second heat shield is disposed to cover said second stage [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 27, Vogman and Kinnard teach the apparatus of claim 8, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said pair of first stages and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage [based on the claim interpretation indicated in the USC 112 rejection above, this limitation further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
As per claim 28, Vogman and Kinnard teach the apparatus of claim 8, wherein said apparatus is configured for providing continuity of power to said IT equipment, wherein said electrical power comprises first and second power sources that operate independently of each other [Kinnard FIG. 2 (main input and aux input are independent power sources)], wherein said second power path maintains a connection between said second power source and said IT equipment while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said IT equipment while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational [Kinnard 0036: (power sources are isolated from each other and maintain configuration even if a power source fails; there is no disconnection performed based on failure and thus connections are maintained)], wherein said first stages of said first and second power paths are non-isolated from each other [Kinnard FIG. 4: (in certain configurations, a single source may provide power to more than one PFC stage as shown with AC source A; the PFC stage of 432 is not isolated from the PFC stage of 434 because they share the same power source)].
As per claim 29, Vogman and Kinnard teach the apparatus of claim 8, wherein said power supply comprises a package that is insertable between said electrical power and said motherboard, wherein said pair of first stages is disposed within said package, and wherein said second stage is disposed or packaged alone on said motherboard along with said load circuitry [the claim indicates second stage is on motherboard; this claim further limits an alternative limitation in claim 1, but the other alternative limitation has already been rejected; therefore, this claim is rejected due to the rejection of the other alternative limitation in claim 1].
Claim 30 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim(s) 4 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogman PGPUB 2014/0001871 in view of Kinnard PGPUB 2013/0020872, and further in view of Yamada1 PGPUB 2016/0065077.
As per claim 4, Vogman and Kinnard teach the apparatus of claim 1.
Vogman and Kinnard do not teach wherein said first stage comprises capacitors and transformers that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors. Although Kinnard describes a capacitor in the first stage that sustains the voltage, Kinnard does not describe a plurality of capacitors and transformers.
Yamada teaches AC-DC conversion circuit that is well known as a power factor correction circuit in the art. Thus Yamada is similar to Vogman and Kinnard because they teach an AC-DC conversion circuit that provides power factor correction. Yamada further teaches wherein said first stage comprises capacitors and transformers [FIG. 3 capacitors 9 and transformers 32], that collectively sustain a voltage equal to that provided by a source of said electrical power [FIG. 3: (they collectively sustain voltage equal to that provided by AC power source 1)], wherein each of said input capacitors sustains a fraction of said voltage [FIG. 3: (capacitors connected in series with AC power source; thus each capacitors only has a fraction of the voltage provided from the power source)], wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers [FIG. 3: (each capacitor 9a-c is connected to its own transformer 32a-c)], wherein said primary windings are cascaded [FIG. 3: (transformers are next to each other and connected in series)], and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors [FIG. 3 and 0022: (secondary side of transformers are connected and tied together, and transformers are isolation transformers; thus second stage voltage is sum of that across each of the capacitors)].
The combination of Vogman and Kinnard with Yamada leads to implementation of multiple transformers and capacitors in the power factor correction stage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Yamada’s teachings of transformer and capacitor connections in the PFC stage of Vogman and Kinnard. One of ordinary skill in the art would have been motivated to provide the described transformer and capacitor connections in Vogman and Kinnard because such connections between capacitors and transformers are conventional in DC power supply equipment [Yamada 0005] and the modifications described by Yamada reduces fixed loss [Yamada 0015 and 0021], thereby improving efficiency of the power supply in Vogman and Kinnard. Having multiple capacitors and transformers improves the redundancy and allows for continued transmission of power in the event a capacitor or transformer fails.
As per claim 25, Vogman and Kinnard teach the apparatus of claim 8.
Vogman and Kinnard do not teach wherein said first stage comprises capacitors and transformers, that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors. Although Kinnard describes a capacitor in the first stage that sustains the voltage, Kinnard does not describe a plurality of capacitors and transformers.
Yamada teaches AC-DC conversion circuit that is well known as a power factor correction circuit in the art. Thus Yamada is similar to Vogman and Kinnard because they teach an AC-DC conversion circuit that provides power factor correction. Yamada further teaches wherein said first stage comprises capacitors and transformers [FIG. 3 capacitors 9 and transformers 32], that collectively sustain a voltage equal to that provided by a source of said electrical power [FIG. 3: (they collectively sustain voltage equal to that provided by AC power source 1)], wherein each of said input capacitors sustains a fraction of said voltage [FIG. 3: (capacitors connected in series with AC power source; thus each capacitors only has a fraction of the voltage provided from the power source)], wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers [FIG. 3: (each capacitor 9a-c is connected to its own transformer 32a-c)], wherein said primary windings are cascaded [FIG. 3: (transformers are next to each other and connected in series)], and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors [FIG. 3 and 0022: (secondary side of transformers are connected and tied together, and transformers are isolation transformers; thus second stage voltage is sum of that across each of the capacitors)].
The combination of Vogman and Kinnard with Yamada leads to implementation of multiple transformers and capacitors in the power factor correction stage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Yamada’s teachings of transformer and capacitor connections in the PFC stage of Vogman and Kinnard. One of ordinary skill in the art would have been motivated to provide the described transformer and capacitor connections in Vogman and Kinnard because such connections between capacitors and transformers are conventional in DC power supply equipment [Yamada 0005] and the modifications described by Yamada reduces fixed loss [Yamada 0015 and 0021], thereby improving efficiency of the power supply in Vogman and Kinnard. Having multiple capacitors and transformers improves the redundancy and allows for continued transmission of power in the event a capacitor or transformer fails.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogman PGPUB 2014/0001871 in view of Kinnard PGPUB 2013/0020872, and further in view of Wyma1 PGPUB 2019/0103761 and Meinecke et al. (hereinafter as Meinecke1) PGPUB 2015/0245531.
As per claim 11, Vogman and Kinnard teach the apparatus of claim 8.
Vogman and Kinnard do not teach wherein said pair of first stages and said second stage are hot swappable independently of each other. Although they teach implementation of the stages on ASIC chips, they do not indicate they are hot swappable.
Wyma teaches modular power supply system with AC/DC rectifiers to provide power to servers. Wyma is thus similar to Vogman and Kinnard because they teach an AC/DC converter (along with PFC circuitry). Wyma further teaches the pair of first stages is hot- swappable [0010 and claim 2: (multiple AC/DC rectifiers (pair of first stages) are hot-swappable for mains converter)]. Wyma teaches that AC/DC rectifiers are hot swappable.
The combination Vogman and Kinnard with Wyma leads to the AC-DC stage components in the power supply of Vogman and Kinnard to be hot-swappable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Wyma’s teachings of the AC/DC rectifier being hot-swappable in Vogman and Kinnard. One of ordinary skill in the art would have been motivated to provide hot-swappable rectifiers in Vogman and Kinnard because it allows for easy replacement of damaged rectifiers without interrupting power to server loads, thereby reducing down time.
Vogman, Kinnard, and Wyma do not teach said second stage is hot swappable independently of first stages. Vogman, Kinnard, and Wyma do not describe hot swappable DC-DC converters (second stage).
Meinecke teaches power supply to servers. Meinecke is thus similar to Vogman, Kinnard, and Wyma. Meinecke further teaches second stage is hot swappable [0050: (DC-DC conversion circuits are hot-swappable)].
The combination of Vogman, Kinnard, and Wyma with Meinecke leads to any of the second stage DC-DC converters in Vogman, Kinnard, and Wyma being hot-swappable as well. Hot-swapping a DC-DC converter does not require hot-swapping an AC-DC converter. Thus the combination of Vogman, Kinnard, and Wyma with Meinecke would teach wherein said pair of first stages and said second stage are hot swappable independently of each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Meinecke’s teachings of hot swapping the second stage in Vogman and Kinnard. One of ordinary skill in the art would have been motivated to provide hot-swappable DC-DC converters in Vogman and Kinnard because it allows for easy replacement of damaged DC-DC converters, thereby reducing down time. One of ordinary skill in the art would have been motivated to hot swap DC-DC converters independently from hot-swapping the rectifier (and the corresponding PFC) because it allows for quick and easy replacement of broken or failed stages, without needing to make adjustments to the other stage, thereby saving time and resources.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogman PGPUB 2014/0001871 in view of Kinnard PGPUB 2013/0020872, and further in view of Hung et al. (hereinafter as Hung) PGPUB 2017/0329380.
As per claim 13, Vogman and Kinnard teach the apparatus of claim 8.
Vogman and Kinnard do not explicitly teach wherein said first and second power paths share a common inductor.
Hung teaches a power distribution system for providing power to a server using PFC [FIG. 2 PFC 229] and DC-DC converter [FIG. 2 DC-DC 290] stages. Hung is thus similar to Vogman and Kinnard. Hung further teaches wherein said first and second power paths share a common inductor. Hung further teaches wherein said first and second power paths share a common inductor [FIG. 2: (inductor 274 is shared between PFC 229 and DC-DC converter)].
The combination of Vogman and Kinnard with Hung allows an inductor to be placed between PFC and DC-DC converter stage to store energy and extend hold-up time in Vogman and Kinnard.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Hung’s teachings placing an inductor between PFC and DC-DC converter stages in Vogman and Kinnard. One of ordinary skill in the art would have been motivated to do so in Vogman and Kinnard because the inductor is used to store energy and extend hold up times, thus extending the hold up time, which improves backup power operations and allows for critical operations to be performed [Hung 0004].
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogman PGPUB 2014/0001871 in view of Kinnard PGPUB 2013/0020872, and further in view of Paulsen et al. (hereinafter as Paulsen) PGPUB 2019/0013583.
As per claim 18, Vogman and Kinnard teach the apparatus of claim 8, wherein said electrical power comprises power sources that work independently of each other [Kinnard 0007, 0049, claim 7, and FIG. 5: (independent AC source A and source B)], wherein each of said first stages of said first and second power paths comprises a primary winding [Kinnard FIG. 5: (PFC of top and bottom paths (first and second paths) of PSU 502 each include a primary winding of a transformer)].
Vogman and Kinnard do not explicitly teach a transistor, wherein said transistor connects a corresponding one of said power sources to said primary winding, and wherein said power supply further comprises a controller that controls both of said transistors.
Paulsen teaches circuitry having multiple PFC units and multiple sources [FIG. 2 and FIG. 3]. Paulsen is thus similar to Vogman and Kinnard because they teach having multiple power sources each providing power to a PFC unit through its own power path. Paulsen further teaches each first stage comprises teach a transistor [FIG. 2 solid state current breaker 156a and 156b], wherein said transistor connects a corresponding one of said power sources to said primary winding [FIG. 1 and FIG. 2, and 0030: (solid state current breaker connects power source to connector 172 which provides power to distribution circuit 108 that is connected to transformer primary windings)], and wherein said power supply further comprises a controller that controls both of said transistors [0029 and FIG. 2: (control 160 controls both of the 2 solid state current breaker 156a and 156b)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Paulsen’s teachings of each power path having a transistor switch to connect to the transformer winding and controlled by a single controller in Vogman and Kinnard. One of ordinary skill in the art would have been motivated to have such an arrangement in Vogman and Kinnard to selectively enable or disable with power path to use to provide power to the load, thus providing greater control over which power source to use.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogman PGPUB 2014/0001871 in view of Kinnard PGPUB 2013/0020872, and further in view of Tanaka PGPUB 2012/0001599.
As per claim 23, Vogman and Kinnard teach the apparatus of claim 8.
Vogman and Kinnard do not teach wherein said electrical power comprises dc power and wherein, when said power supply is connected to said dc power, said first stage is bypassed.
Tanaka teaches power supply circuitry for a computing load and describes PFC circuitry being used with DC/DC converter circuitry. Tanaka is thus similar to Vogman and Kinnard. Tanaka further teaches wherein said electrical power comprises dc power [0071-0073: (input power is DC)] and wherein, when said power supply is connected to said dc power, said first stage is bypassed [0078: (PFC circuit is bypassed and input DC power is converted by the DC/DC converter)].
The combination of Vogman and Kinnard and Tanaka allows DC power to be used as an input power, and lets the PFC be bypasses when the DC power is input.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Tanaka’s teachings of providing a DC input and bypassing the PFC circuit when DC input is used in Vogman and Kinnard. One of ordinary skill in the art would have been motivated to have the power supplies in Vogman and Kinnard be able to accept both AC and DC power as input because it improves the power supply’s flexibility in what kind of power sources it can accept, and thus improve reliability by having more backup power sources. One of ordinary skill in the art would have been motivated to bypass the PFC circuit when DC power is input because power factor correction is unnecessary on DC power sources, thus saving resources and reducing waste.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Kociecki (USPAT 6,198,642) teaches power supplies are insertable by hand and can be mounted [col. 4 lines 28-30], and in primary domain, power supplies each have PFC 192 and in secondary domain that is the same as main control board, there are various DC-DC converters [FIG. 6].
Yu et al. (PGPUB 2022/0200483) teaches DC power bypassing PFC converter [0035].
Walker (PGPUB 2020/0249736) indicates PFC controller may be a discrete IC.
Song et al. (PGPUB 2020/0146174) teaches PFC in the form of an inductor and capacitor positioned on the motherboard [0039], and not in the form of a package.
Livescu et al. (USPAT 10,560,015) teaches multiple PFC stages connected to DC/DC converter stages.
You et al. (USPAT 10,256,716) indicates PFC is formed on an IC.
Lee et al. (PGPUB 2017/0038823) teaches a PFC IC on a power supply.
Loffink et al. (PGPUB 2007/0170783) teaches power supply with multiple inputs and may include PFC and DC-DC converter [0006 and FIG. 1].
Atluri et al. (PGPUB 2006/0226705) teaches removable and insertable hot-pluggable power supplies.
Lu et al. (PGPUB 2010/0165679) teaches two PFC circuits connecting to a sing DC-DC converting circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
1 Cited in IDS on 12/05/2024
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