DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to because:
Figure 1 is objected to because it shows block but does not indicate what is each block and this does not help to understand what the figure is intended to; it is suggested to indicate what each block is.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “601” (see figure 6).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure filed on 12/05/2024 is accepted by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 8-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dvir (US 20080124092 A1).
Regarding claim 1, Dvir discloses an optical receiver, configured to receive optical burst signals in a passive optical network, PON (abstract "BCDR" “Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information”, paragraphs [0002]-[0007], figures 3-4) the optical receiver comprises a clock-and-data-recovery, CDR, circuitry configured to synchronise a reference clock signal (Figure 3 block 302) with a received optical burst signal starting from a configurable initial clock phase, to obtain a synchronised data signal and a synchronised clock phase, the optical receiver further comprises a phase estimation circuitry (Figure 3 block 330) configured to estimate a phase of a received optical burst signal with respect to the reference clock signal, the optical receiver is further configured to (abstract figure 3-4 paragraphs [0035]-[0039]); during receiving of a first optical burst signal, estimate, by the phase estimation circuitry, at least a first phase estimate, and synchronise, by the CDR circuitry, the reference clock signal with the first optical burst signal, thereby obtaining a first synchronised clock phase ("BCDR", ,[0040]- [0042] “the acquisition of the phase information for each ONU is performed during the set-up mode of operation, which takes place during the activation procedures of an ONU” … “The digital filter 340 compares the extracted phase information to the phase of the respective current transmitting ONU as stored in the memory 352. If the comparison results in inequality, the extracted phase information is saved in the memory 352 and sent to the phase interpolator 320 for future sampling of the input data signal 301 to recover the data in that signal; otherwise, data is sampled using the previous generated sampling signals”); determine a phase estimate correction based on a difference between the first synchronised clock phase and the first phase estimate (abstract figure 3 paragraphs [0035]-[0037] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350”); and during receiving of a second optical burst signal, estimate, by the phase estimation circuitry, a second phase estimate correct the second phase estimate with the phase estimate correction, to obtain a corrected phase estimate and, by the CDR circuitry, synchronise the reference clock signal with the corrected phase estimate as the configurable initial clock phase (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320.”)
PNG
media_image1.png
426
569
media_image1.png
Greyscale
Regarding claim 15, Dvir discloses during receiving of a first optical burst signal, estimate, by the phase estimation circuitry, at least a first phase estimate, and synchronise, by the CDR circuitry, the reference clock signal with the first optical burst signal, thereby obtaining a first synchronised clock phase (abstract "BCDR" “Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information”, paragraphs [0040]- [0042] “the acquisition of the phase information for each ONU is performed during the set-up mode of operation, which takes place during the activation procedures of an ONU” … “The digital filter 340 compares the extracted phase information to the phase of the respective current transmitting ONU as stored in the memory 352. If the comparison results in inequality, the extracted phase information is saved in the memory 352 and sent to the phase interpolator 320 for future sampling of the input data signal 301 to recover the data in that signal; otherwise, data is sampled using the previous generated sampling signals”); determine a phase estimate correction based on a difference between the first synchronised clock phase and the first phase estimate (abstract figure 3 paragraphs [0035]-[0037] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350”); and during receiving of a second optical burst signal, estimate, by the phase estimation circuitry, a second phase estimate correct the second phase estimate with the phase estimate correction, to obtain a corrected phase estimate and, by the CDR circuitry, synchronise the reference clock signal with the corrected phase estimate as the configurable initial clock phase (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350. The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320.”)
Regarding claim 2, Amir discloses claim 1, Amir also discloses equalisation circuitry configured to perform equalisation by applying equalisation coefficients on received optical burst signals (abstract figure 3 paragraphs [0035]-[0047] block 340 "The digital filter 340 compares the extracted phase information to the phase of the respective current transmitting ONU as stored in the memory 352. If the comparison results in inequality, the extracted phase information is saved in the memory 352 and sent to the phase interpolator 320 for future sampling of the input data signal 301 to recover the data in that signal; otherwise, data is sampled using the previous generated sampling signals” … “the digital filter 340 instructs the phase interpolator 320 to shift the clock signals 301 by b/k, where b represents the number of phase errors detected by the PEU 330 at the sampling point and k is the maximum number of possible phase error that can be detected in a single clock cycle.”)
Regarding claim 3, Amir discloses claim 1, Amir also discloses during the receiving of the first optical burst signal, the first phase estimate is used for determining the configurable initial clock phase of the CDR for the synchronizing (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350. The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320.”)
Regarding claim 4, Amir discloses claim 1, Amir also discloses estimate, by the phase estimation circuitry, an initial phase estimate performed after starting the synchronising and used for determining the configurable initial clock phase of the CDR for the synchronising (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350. The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320.”)
Regarding claim 5, Amir discloses claim 4, Amir also discloses estimating the first phase estimate is performed while performing the synchronising (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350. The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320.”)
Regarding claim 8, Amir discloses claim 4, Amir also discloses locking the reference clock signal to the received optical burst signal, to establish the synchronised clock phase and tracking the received optical burst signal, to adjust the synchronised clock phase, the estimating of the first phase estimate is performed after the locking (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350. The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320.”)
Regarding claim 9, Amir discloses claim 4, Amir also discloses the phase estimate correction is further based on phase estimate corrections determined for one or more further previously received optical burst signals (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350”)
Regarding claim 10, Amir discloses claim 1, Amir also discloses estimate, by the phase estimation circuitry, an initial phase estimate performed after starting the synchronising and used for determining the configurable initial clock phase of the CDR for the synchronising (abstract figure 3 paragraphs [0035]-[0047] "The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350. The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320.”)
Regarding claim 11, Amir discloses claim 1, Amir also discloses received optical burst signals comprise a preamble pattern, a delimiter and payload symbols, and wherein the CDR circuitry and phase estimation circuitry are configured to operate at least on the preamble pattern, wherein the preamble pattern comprises a first pattern and a second pattern, and wherein the CDR circuitry is configured to operate on the first pattern and the phase estimation circuitry is configured to operate on the second pattern (abstract figure 3 paragraphs [0035]-[0047] " The burst detector 370 detects, with high accuracy, an incoming burst data during the set-up mode. A burst data is received in a form of a cell, which includes a preamble and data portions. The preamble has a predefined pattern of bits (e.g., [0101010101]) and its length is greater than `m` bytes (m>2). The burst detector 370 processes sampled data streams 304 and tries to detect two types of events: a) a preamble pattern, and b) number of transitions. The burst detector 370 searches for a preamble pattern in each of the data streams. If a pattern is detected in any of the streams and within a predefined limit of length, then a preamble detected signal is asserted. The burst detector 370 further counts the number of transitions from `1` to `0` and from `0` to `1` in all sampling streams 304 during a predefined time interval. If the total count is within a predefined threshold a burst detection signal is asserted. The burst detector 370 can further assert a detection signal based on any combination of the two detection signals”)
Regarding claim 12, Amir discloses claim 4, Amir also discloses estimating the first phase estimate is performed by executing a first estimation algorithm selected such that a variance error of the first estimation algorithm is smaller than a variance error of the initial estimation algorithm, and estimating the initial phase estimate is performed by executing an initial estimation algorithm (abstract figure 3 paragraphs [0035]-[0047] "the digital filter 340 instructs the phase interpolator 320 to shift the clock signals 301 by b/k, where b represents the number of phase errors detected by the PEU 330 at the sampling point and k is the maximum number of possible phase error that can be detected in a single clock cycle.”)
Regarding claim 13, Amir discloses claim 1, Amir also discloses on optical line terminal, OLT, comprising the optical receiver according to claim 1; wherein the optical receiver is configured to receive optical burst signals from a plurality of optical network units, ONUs (abstract figure 3 paragraphs [0035]-[0047] "FIG. 3 is a block diagram of a burst mode clock and data recovery (BCDR) circuit 300 implemented in accordance with one non-limiting embodiment of the present invention. The BCDR circuit 300 includes an over-sampler 310, a phase interpolator 320, a phase estimation unit (PEU) 330, a digital filter 340, a phase retrieval unit 350, and a pipeline 360. In one embodiment, the BCDR circuit 300 is installed in an OLT (e.g., OLT 130) and adapted to receive burst data sent from ONUs (e.g., ONUs 120) over the common channel”)
Regarding claim 14, Amir discloses claim 13, Amir also discloses perform the determining of the phase estimate correction and the correcting of the second phase estimate based on optical burst signals obtained from a same ONU (abstract figure 3 paragraphs [0035]-[0047] " The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350”).
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Amendments received before examination dated 12/15/2025 for EP 23218047.
Amended claims with annotations dated 12/15/2025 for EP 23218047.
European search report dated 06/14/2024 for EP 23218047.
European search opinion dated 06/14/2024 for EP 23218047.
Suvakovic (US 20090279886 A1) discloses burst-mode data recovery for multi-gigabit passive optical networks.
Kaneda (US 20190334627 A1) discloses clock recovery for band-limited optical channels.
Wu (US 11509395 B2) discloses data transmission method, related apparatus, and system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUAN A TORRES whose telephone number is (571) 272-3119. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth N Vanderpuye can be reached at (571) 272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUAN A TORRES/ Primary Examiner, Art Unit 2634
Prosecution Insights