DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 12/05/2024. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Loprieno (US 2019/0097748 A1) and further in view of Nicholl (“Details of 4-lane Interleaved 100G FEC”, IEEE P802.3ck Ad Hoc, April 24, 2019).
Claim 1: Loprieno teaches a method comprising:
obtaining a stream of bits received for at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed (e.g., ¶[0027], Fig. 3: “At 350, process 304 forms individual PCS lanes from the multiple (receive) PCS lanes… At 352, the PCS lanes, including the FEC codewords, are reordered and deinterleaved.” De-interleaving inherently recovers logical lanes from a physical lane), which plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes that was bit-multiplexed to the at least one physical lane (e.g., implied by the existence of a transmit-side mapping (¶[0029] – “reverse of transmit process”);
storing the re-ordered block of bits obtained from the plurality of modified logical lanes to a memory (e.g., ¶[0027]: “process 304 removes the modified AM groups from the sequence of decoded bit blocks, and stores in memory the security information.” Although security info is the example, storing data blocks before further processing is inherent in any PCS receive pipeline);
performing an inverse of the mapping on the re-ordered block of bits stored in the memory to obtain the original block of bits (e.g., ¶[0030], Fig. 3, blocks 352 “Lane reorder and de-interleave”, 356 “Post FEC interleave”, 364 “remove security protection”. Reversing transmit-side mapping is implicit – the specification states that receive process is “for the most part, the reverse of transmit process” -¶[0029]); and
distributing the original block of bits to the plurality of logical lanes (e.g., ¶[0030], Fig. 3, block 370 “Decoder and rate matcher” produces CCMII/CDMII data octets, which are distributed to logical lanes).
Not explicitly taught by Loprieno is the specific interleaving pattern where a physical lane contains “a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword”. However, Nicholl teaches, in page 11, that “10-bit symbols are interleaved onto FEC lanes in the same manner as CL119 – ‘A’ character below represents a 10-bit symbol from codeword A – ‘B’ character below represents a 10-bit symbol from codeword B - ABABBABAABABBABA…ABABBABA”. Nicholl also teaches, in page 12, that “10-bit symbols are de-interleaved from FEC lanes in the same manner as CL119… ABABBABAABABBABA…ABABBABA”. This directly describes the receive-side de-interleaving that corresponds to the claimed “sequence of groups … from one FEC codeword followed by a sequence … from another FEC codeword”. Nicholl further states that its architecture “heavily leverages existing CL91 and CL119” (page 5), confirming that the interleaving pattern is a known, standard feature of 200/400GbE PCS.
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a POSITA designing a PCS receiver to consult the transmit-side specification, including proposals such as Nicholl, to determine how symbols are interleaved onto physical lanes. Because the receiver must perform the inverse operation, a skill artisan would have been motivated to take Loprieno’s generic “de-interleave” step and implement it with the specific ABAB pattern taught by Nicholl in order to correct decoding of the transmitted data.
Claim 2: Loprieno and Nicholl teach the method of claim 1, wherein obtaining comprises obtaining streams of bits received for each of a plurality of physical lanes from which the plurality of modified logical lanes have been de-multiplexed. For instance, Loprieno’s Fig. 3 and ¶[0027] describe “multiple PCS lanes” (8 or 16 lanes).
Claim 3: Loprieno and Nicholl teach the method of claim 2, further comprising: prior to storing, deskewing the streams of bits of the plurality of physical lanes (e.g., Loprieno: ¶[0027], Fig. 3, block 350 “Alignment lock and deskew”).
Claim 4: Loprieno and Nicholl teach the method of claim 3, further comprising: determining an alignment marker for bits of the plurality of logical lanes (e.g., Loprieno: ¶[0022] “process 302 periodically inserts AM groups into the sequence of scrambled bit blocks… Each AM group includes individual AMs for respective ones of the multiple lane… The individual AMs support deskew and reordering of the individual PCS lanes in receive process 304”); and adjusting the deskewing until alignment marker lock is successful (e.g., Loprieno: ¶[0027] process 304 forms individual PCS lanes from the multiple (receive) PCS lanes, and obtains lock on the individual AMs in each PCS lane. Once lock is achieved, process 302 removes inter-lane skew, i.e., deskews the PCS lanes).
Claim 5: Loprieno and Nicholl teach the method of claim 1, wherein each group in the sequence of groups is two or more bits (e.g., Loprieno: ¶[0026] – “At 344, process 302 distributes and interleaves the multiple FEC codewords across the multiple PCS lanes”).
Claims 6-10, are directed to an apparatus embodiments that correspond to the method claims of claims 1-5. Accordingly, claims 6-10 are rejected on same grounds as claims 1-5.
Claim(s) 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Loprieno (US 2019/0097748 A1) and further in view of 25G/50G Ethernet Consortium’s Low Latency Reed Solomon Forward Error Correction Specification (“LL-FEC Specification”, 2018).
Claim 11: Loprieno teaches a method performed by a first device that is in communication with a second device, comprising:
configuring a transmit function to use a modified bit ordering that maps bits from a plurality of logical lanes to a plurality of modified logical lanes that are bit-multiplexed to at least one physical lane for transmission to a second device (e.g., ¶[0026]-[0027], Fig. 3 - blocks 302-344). The transmit process adds security protection (a modified format) and performs symbol distribution and FEC encoding, which inherently involves mapping logical lanes (PCS lanes) to physical lanes. The “modified bit ordering” is the security-protected frame format that differs from a standard (un-modified) Ethernet frame);
configuring a receive function to use a modified bit ordering for processing a stream of bits received from the second device on at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, the plurality of modified logical lanes being equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to the modified bit ordering (e.g., ¶[0027]-[0030], Fig. 3 (blocks 350-370). The receive process is “the reverse of transmit process” and is configured to handle the security-protected (modified) frames. It de-multiplexes physical lanes into logical lanes and reverses the mapping);
receiving an incoming bit stream from the second device (e.g. ¶[0027] (“receives multiple PCS lanes transmitted by a …”); and
attempting to process the incoming bit stream from the second device with the receive function using the modified bit ordering (e.g., implicit in the operation of the receive process – it naturally attempts to decode using its configured (modified) format).
Not explicitly taught by Loprieno is when processing the incoming bit stream using the modified bit ordering is not successful, configuring the receive function of the first device to use an un-modified bit ordering for processing the incoming bit stream from the second device.
However, Section 3.5 (“Autonegotiation”) of the LL-FEC Specification (pages 7-8) describes a mechanism for two link partners to negotiate whether to use a modified forward error correction (RS(272) LL-FEC) or the standard RS(544) FEC. And Section 3.5.2 (“Autonegotiation Resolution”) provides pseudocode that determines whether to operate with the modified (LL-FEC) or un-modified (standard IEEE) FEC. Specifically: “IF ((HCD == IEEE 200GBASE-KR4/CR4) & (LD.LF3 & RD.LF3) & (LD.LFR | RD.LFR)) THEN operate as 200GBASE-KR4/CR4, substituting RS(272) FEC for RS(544) FEC” – this is a direct teaching of attempting to use a modified bit ordering (RS(272) based) and, under conditions (e.g., failure or lack of mutual capability), falling back to the un-modified standard (RS(544)).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a POSITA designing a receiver that supports a non-standard (modified) bit ordering to recognize that not all link partners may support that modification and to include a fallback mechanism that reverts to a standard, un-modified bit ordering in order to maintain interoperability.
Claim 12: Loprieno and LL-FEC Specification teach the method of claim 11, further comprising: attempting to process the incoming bit stream with the receive function using the un-modified bit ordering; and when processing the incoming bit stream using the un-modified bit ordering is successful, configuring the transmit function to use the un-modified bit ordering for transmissions to the second device. For instance, the LL-FEC Specification explicitly teaches that if the remote device does not support the modified mode (or if negotiation fails), the link operates in the un-modified (standard) mode. This necessarily includes attempting the un-modified ordering and, upon success, configuring the transmit function accordingly
Claim 13: Loprieno and LL-FEC Specification teach the method of claim 11, when processing the incoming bit stream using the modified bit ordering is successful, continuing to use the modified bit ordering with the receive function for processing transmissions received from the second device (e.g., This is inherent in the autonegotiation resolution taught by the LL-FEC Specification (e.g., if both sides support LL-FEC, they operate with RS(272)).
Claim 14: Loprieno and LL-FEC Specification teach the method of claim 11, wherein receiving the incoming bit stream comprises receiving streams of bits received for each of a plurality of physical lanes from which the plurality of modified logical lanes have been de-multiplexed. For instance, Loprieno’s Fig. 3 shows multiple PCS lanes (8 for 200GbE, 16 for 400GbE).
Claim 15: Loprieno and LL-FEC Specification teach the method of claim 14, further comprising: deskewing the streams of bits of the plurality of physical lanes. For instance, Loprieno ¶[0027] explicitly teaches “alignment lock and deskew” (block 350).
Claim 16: Loprieno and LL-FEC Specification teach the method of claim 15, further comprising: determining an alignment marker for bits of the plurality of logical lanes (e.g., Loprieno: ¶[0022] “process 302 periodically inserts AM groups into the sequence of scrambled bit blocks… Each AM group includes individual AMs for respective ones of the multiple lane… The individual AMs support deskew and reordering of the individual PCS lanes in receive process 304”); and adjusting the deskewing until alignment marker lock is successful (e.g., Loprieno: ¶[0027] process 304 forms individual PCS lanes from the multiple (receive) PCS lanes, and obtains lock on the individual AMs in each PCS lane. Once lock is achieved, process 302 removes inter-lane skew, i.e., deskews the PCS lanes).
Claims 17-20, are directed to an apparatus embodiments that correspond to the method claims of claims 11-14. Accordingly, claims 17-20 are rejected on same grounds as claims 11-14.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 5/12/2026
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