DETAILED ACTION
This action is responsive to the response filed 5 Dec 2024 and the Information Disclosure Statement filed 5 Dec 2024. Claims 1-18 are pending. Claim 1 is independent.
The office action includes a section 112(b) rejection and non-statutory obvious double patenting rejection in addition to the section 102/103 rejections.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5 Dec 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Examiner Note
This office action has two rejections for claim 1. BOTH rejections must be addressed in a response. The present application has used the limitation of “DRAM” without further limiting DRAM to a 1 transistor, 1 capacitor construction. Hariri has been introduced as a DRAM-structure using thin film transistors. To overcome the Hariri rejection, applicant must specify that the DRAM comprises 1T1C construction.
The present application has used the limitation of “comprising”. The examiner notes that MPEP 2111.03 states, “The transitional term “comprising”, which is synonymous with “including,” “containing,” or “characterized by,” is inclusive or open-ended and does not exclude additional, unrecited elements or method steps.” The MPEP 2111.03 later states, “The transitional phrase “consisting of” excludes any element, step, or ingredient not specified in the claim.
The present application has used the limitation of “associated with”. This has been interpreted as simply residing withing the same device without reference to any connections between devices.
The present application has used the limitation of “first axis, second axis, third axis”. The examiner notes that typical 3D construction has word lines across the top of a structure in an X or Y direction, has vias in the periphery which penetrate in the Z direction to the appropriate “step” or plane of memory, and then extends in an X or Y direction to include multiple memory cells within the memory array proper. Thus, typical word lines, unless further limited to include connections between memory cells, can comprise coupled structures in all three dimensions.
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/969,177 in view of Simsek.
This is a provisional nonstatutory double patenting rejection.
18/970,119: Present Applications
18/969,177: Co-pending
Rationale
1. A dynamic random access memory, DRAM, comprising: a block comprising a 3D array of memory cells;
wherein the block comprises multiple planes stacked along a first axis, each plane comprising a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and the second axis; and
wherein the block is divided into multiple sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane;
the DRAM further comprising: a plurality of bit lines, wherein each bit line extends along the third axis in one of the planes and is connected to one column of memory cells in that plane, or wherein each bit line extends in one of the planes along the second axis and is connected to one memory cell in each sub-block;
a plurality of global bit lines, wherein the global bit lines are connected to the bit lines in each sub-block; and
a plurality of sense amplifiers, wherein each sense amplifier is connected to one of the global bit lines.
1. A dynamic random access memory comprising: a block comprising a three-dimensional array of memory cells; wherein the block comprises planes stacked along a first axis, each of the planes comprising a two-dimensional array of the memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first axis and the second axis,
wherein the block is divided into multiple sub-blocks arranged along the second axis, wherein each of the sub-blocks contains one of the columns of the memory cells of each of the planes;
the dynamic random access memory further comprising: local bit lines each extending along the first axis in one of the sub-blocks and connected to one memory cell in each of the planes;
global bit lines, wherein one or more of the global bit lines are connected to the local bit lines in each of the sub-blocks; and
sense amplifiers each connected to one of the global bit lines.
Simesek, 2024/0074142
has been used to teach any elements that are not identical.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 5, 10, 11, 15, and 16 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 5, 10, and 15 recites the limitation, “arranged sequentially” Claim 5, 11, and 16 recite the limitation “arranged interleaved”.
The phrase "arranged sequentially" is indefinite because the numbering or labeling of components such as bit lines, word lines, and sub-blocks is arbitrary. It would be clearer to use claim language to specify that a consecutive group of the components are all connected in common to another component. The phrase "arranged interleaved" is also indefinite for the same reasons; while interleaved indicates an alternating pattern, the claim language does not provide clarity on what it means for the group of components to be interleaved. Examiner recommends amended these claims to provide clarity
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hariri, et. al., U.S. Patent Application Publication 2019/0319044
Regarding claim 1, Hariri teaches:
A dynamic random access memory, DRAM, comprising: a block comprising a 3D array of memory cells; (Harari, fig 1a , "[0024] However, as the refreshing required of a vertical NOR string array is expected to be much less frequently than in a conventional dynamic random-access memory (DRAM), the multi-gate NOR string arrays of the present invention may operate in some DRAM applications. Such use of the vertical NOR strings allows a substantially lower cost-per-bit figure of merit, as compared to conventional DRAMs, and a substantially lower read latency, as compared to conventional NAND string arrays."; a DRAM circuit comprising stacks of NOR memory instead of conventional DRAM of 1T1C construction.)
wherein the block comprises multiple planes stacked along a first axis, each plane comprising a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and the second axis; and wherein the block is divided into multiple sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane; (Harari, fig 4a-4c, 6a-g, "[0068] FIG. 4c shows a basic circuit representation in the Z-X plane of vertical NOR string pairs 491 and 492, according to one embodiment of the present invention."; that two planes of NOR gates can be used with multiple perpendicular rows and columns as claimed.)
the DRAM further comprising: a plurality of bit lines, wherein each bit line extends along the third axis in one of the planes and is connected to one column of memory cells in that plane, or wherein each bit line extends in one of the planes along the second axis and is connected to one memory cell in each sub-block; a plurality of global bit lines, wherein the global bit lines are connected to the bit lines in each sub-block; and (Harari, fig 4a-4c, 6a-g, "FIG. 4a indicates by dashed boxes 416 the locations where nonvolatile storage elements (or storage transistors) T0 to T31 may be formed. Dashed box 470 indicates where a dedicated pre-charge transistor may be formed, which, when momentarily switched on, allows charge to be transferred from common local bit line region 454 to common local source line region 455 when all transistors T0 to T31 are in their off state."; figs 4a-4c and figs 6a-g which show three axis construction with plurality of bit liens, that a "sub-block", or single column of memory can comprise multiple memory cells; a global bit line, local bit lines and word lines connected in that column)
the DRAM further comprising: a plurality of bit lines, wherein each bit line extends along the third axis in one of the planes and is connected to one column of memory cells in that plane, or wherein each bit line extends in one of the planes along the second axis and is connected to one memory cell in each sub-block; a plurality of global bit lines, wherein the global bit lines are connected to the bit lines in each sub-block; and (Harari, fig 1a , "[0081] The inventor notes that, with sense amplifiers and other support circuits provided in the semiconductor substrate, routing global bit lines using global interconnect conductors provided above or below a memory array to connect to vertical local bit lines (e.g., global bit line GBLl connecting to the vertical local bit line 554 of FIG. Sa) results in large RC delays because of the substantial length of the wiring involved."; that prior art teaches global bit lines attached to sense amplifiers but introduce substantial wiring lengths.)
Claims 1 – 5, 17, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Simsek-Ege, F., U.S. Patent Application Publication 2024/0074142 (“Simsek”).
Regarding claim 1, Simsek teaches:
A dynamic random access memory, DRAM, comprising: a block comprising a 3D array of memory cells; (Simsek, fig 1A-1R, “[0022] FIG. 1A through FIG. lR are simplified partial top-down views… cross-sectional views… perspective views… a method of forming a first microelectronic device structure 100 ( e.g., a memory device, such as a 3D DRAM memory device),”; a 3D DRAM structure).
wherein the block comprises multiple planes stacked along a first axis, each plane comprising a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and the second axis; and (Simsek, fig 1A-1R, “[0030] With reference to FIG. 1A and FIG. 1B, within the array region 101,… structure 100 includes vertical (e.g., in the Z-direction) stacks of memory cells 120 over a first base structure 110. [0035] Each access device 130 of the vertical stack of access devices 130 individually includes a channel region 134 comprising a channel material 116 in electrical communication with at least a portion of the horizontally neighboring (e.g., in the Y-direction) the storage device 150 (e.g., a first electrode 152 of the horizontally neighboring storage device 150). With reference to FIG. lC, the conductive structures 132 vertically overlying ( e.g., in the Z-direction) and within horizontal boundaries (e.g., in the X-direction, in the Y-direction) of one another may form a vertical stack structure 135 of conductive structures 132.”; a 3D DRAM structure with three axes: memory cells stacked in an planar fashion in the z-direction; “access devices” running in a y-direction, and conductive layers 132 running in the x-direction).
wherein the block is divided into multiple sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane; (Simsek, fig 1M-1N, “[0098] With reference to FIG 1M… In some embodiments, in the cross-sectional illustrated in FIG. lM, every other one of the global digit line contacts structures 186 (e.g., in the X-direction) is a first global digit line contact structure 186A and the other global digit line contact structures 186 is a second global digit line contact structure 186B.”; a memory array 101 area subdivided into multiple 3D volumes with at least two different Global digit lines, each GDL accessing a different column of memory cells).
the DRAM further comprising: a plurality of bit lines, wherein each bit line extends along the third axis in one of the planes and is connected to one column of memory cells in that plane, or wherein each bit line extends in one of the planes along the second axis and is connected to one memory cell in each sub-block; (Simsek, fig 1A-1R, “[0058] With reference to FIG. 1A , FIG. 1B, and FIG. lE, the first microelectronic device structure 100 may include conductive pillar structures 160 vertically (e.g., in the Z-direction) extending through the first microelectronic device structure 100. The conductive pillar structures 160 may also be referred to herein as “digit lines,” “second conductive lines,” “digit line pillar structures,” “local digit lines,” or “vertical digit lines.” The conductive pillar structures 160 may be electrically coupled to the access devices 130 to facilitate operation of the memory cells 120 of a vertical stack of memory cells 120.”; that the DRAM has columns of “digit lines” (i.e. bit lines) that extend in the z-axis (now defined as the third axis)).
a plurality of global bit lines, wherein the global bit lines are connected to the bit lines in each sub-block; and (Simsek, fig 1A-1R, “[0062] In some embodiments, and as described in further detail herein, global digit lines (e.g., first global digit lines 108A (FIG. 1N, FIG. 1P through FIG. lR), second global digit lines 108B (FIG. lN, FIG. 10, FIG. lQ, FIG. lR)) are individually in electrical communication with a multiplexer 166 to selectively couple the global digit line to one of the conductive pillar structures 160 through the multiplexer 166. [0105] With reference to FIG. lN, … portions of the conductive material 185 of the preliminary global digit lines 187 (FIG. lM) to form global digit lines 108 including first global digit lines 108A and the second global digit lines 108B each individually in electrical communication with the global digit line contact structures 186”; that global digit lines (i.e. global bit lines) are connected to local digit lines (i.e. bit lines); sub-blocks are formed by a single column of alternating 130 access devices and 150 storage devices; that two sub-blocks are paired and alternating “global digit lines” 108A and 108B).
a plurality of sense amplifiers, wherein each sense amplifier is connected to one of the global bit lines. (Simsek, fig 2A-2B, “[0122] With reference to FIG. 2A and FIG. 2B. The sense amplifier device regions 202 may include transistor structures in electrical communication with the global digit lines 108 by means of first conductive interconnect structures 204.”; that sense amplifiers 202 can be connected to the global bit lines).
Regarding claim 2, Simsek teaches The DRAM of claim 1, further comprising: a plurality of word lines, wherein each word line extends along the first axis in one of the sub-blocks and is connected to one memory cell in each plane. (Simsek, fig 2A-2C, “[0123] With reference to FIG. 2C, the second microelectronic device structure 250 may include one or more sub word line driver regions 206 vertically overlying ( e.g., in the Z-direction) and within horizontal boundaries of the staircase structures 174. such as vertically overlying the first conductive contact structures 176 and the first pad structures 178.”; that a global word line 206 can be attached to the local word lines using z-direction columns 176 attached to conductor 132, that the conductor 132 transits the X-Y plane; that word line connectors extend in the z-direction to reach the word line plane; that a word line is connected to at least one memory cells in each column (sub-block) of the alternating 108A and 108B; here access devices 130 are assumed the in the y-direction IFF bit line controllers 108A/108B are arranged in the x-direction).
Regarding claim 3, Simsek teaches The DRAM of claim 2, further comprising: a single word line driver shared among all the word lines of the block; or multiple word line drivers, wherein each word line driver is shared among all the word lines of one sub-block. (Simsek, fig 2A-2C, “[0121] By way of non-limiting example, the second microelectronic device structure 250 may include one or more sub word line driver regions [0123] With reference to FIG. 2C, the second microelectronic device structure 250 may include one or more sub word line driver regions 206 vertically overlying ( e.g., in the Z-direction) and within horizontal boundaries of the staircase structures 17 4, such as vertically overlying the first conductive contact structures 176 and the first pad structures 178.”; that at least one word line driver is connected to the “global word line” 206, which is connected to the four layers of access devices 130 in fig 2C; the driver attached to 206 drives all of the word lines of at least one column).
Regarding claim 4, Simsek teaches The DRAM of claim 3, further comprising: one or more word line selectors configured to selectively connect the one or more word line drivers to the word lines; wherein each word line selector comprises a plurality of global word lines, and each global word line is connected to a group of word lines. (Simsek, fig 2A-2C, “[0121] The second microelectronic device structure 250 may include control logic devices ( e.g., CMOS devices) and circuitry configured for … one or more sub word line driver regions… column decoders, multiplexer control logic devices, sense amplifier drivers, main word line driver devices, row decoder devices, and row select devices.”; a main word line driver attached in control structure to sub word line drivers; row decoder and row select devices; as stated above, the stair step device 174 is attached to the access devices 130 (i.e. word lines)).
Regarding claim 5, Simsek teaches The DRAM of claim 4, wherein: each group of word lines comprises word lines that are arranged sequentially along the third axis; or each group of word lines comprises word lines that are arranged sequentially along the second axis; or each group of word lines comprises word lines that are arranged interleaved along the second axis; or each group of word lines comprises word lines that are arranged interleaved along the third axis. (Simsek, fig 2A-2C, “[0121] The second microelectronic device structure 250 may include control logic devices ( e.g., CMOS devices) and circuitry configured for … one or more sub word line driver regions… column decoders, multiplexer control logic devices, sense amplifier drivers, main word line driver devices, row decoder devices, and row select devices. [0123] With reference to FIG. 2C, the second microelectronic device structure 250 may include one or more sub word line driver regions 206 vertically overlying ( e.g., in the Z-direction) and within horizontal boundaries of the staircase structures 174. such as vertically overlying the first conductive contact structures 176 and the first pad structures 178.”; a main word line driver attached in control structure to sub word line drivers; row decoder and row select devices; as stated above, the stair step device 174 is attached to the access devices 130 (i.e. word lines); that the structures 174 are arranged in the z direction (third axis)).
Regarding claim 17, Simsek teaches The DRAM of claim 1, wherein if the bit lines extend along the third axis, each global bit line extends in one of the planes along the second axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] The first global digit line contact structures 186A and the second global digit line contact structures 186B are collectively referred to herein as “global digit line contact structures 186. [0099] The first global digit line contact structures 186A may have a vertical height H2 larger than a vertical height H3 of the second global digit line contact structures 186B.”; that Bit Line groups can be arranged with the Global Bit Lines arranged in the z-direction (i.e. third axis); that with only two groupings, these are arranged “sequentially” and “interleaved”; that the Global BLs are connected to LBLs in the z-direction; that the GBLs are interleaved in the x-direction and extend in the y-direction (i.e. first and second directions)).
Regarding claim 18, Simsek teaches The DRAM of claim 1, wherein if the bit lines extend along the second axis, each global bit line extends in one of the planes along the third axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] The first global digit line contact structures 186A and the second global digit line contact structures 186B are collectively referred to herein as “global digit line contact structures 186. [0099] The first global digit line contact structures 186A may have a vertical height H2 larger than a vertical height H3 of the second global digit line contact structures 186B.”; that Bit Line groups can be arranged with the Global Bit Lines arranged in the z-direction (i.e. third axis) with the 186A higher than the 186B; that with only two groupings, these are arranged “sequentially” and “interleaved”; that the Global BLs are connected to LBLs in the z-direction; that the GBLs are interleaved in the x-direction and extend in the y-direction (i.e. first and second directions)).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 6 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Simsek in view of Murooka, K., U.S. Patent Application Publication 2020/0098827 (“Murooka”).
Regarding claim 6, Simsek teaches the DRAM of claim 2.
Simsek teaches further comprising: a single word line selector shared among all the word lines; or multiple word line selectors, wherein each word line selector is shared among all the word lines of one sub-block; (Simsek, fig 2A-2C, “[0121] The second microelectronic device structure 250 may include control logic devices ( e.g., CMOS devices) and circuitry configured for … one or more sub word line driver regions… column decoders, multiplexer control logic devices, sense amplifier drivers, main word line driver devices, row decoder devices, and row select devices. [0123] With reference to FIG. 2C, the second microelectronic device structure 250 may include one or more sub word line driver regions 206 vertically overlying ( e.g., in the Z-direction) and within horizontal boundaries of the staircase structures 174. such as vertically overlying the first conductive contact structures 176 and the first pad structures 178.”; a main word line driver attached in control structure to sub word line drivers; row decoder and row select devices; as stated above, the stair step device 174 is attached to the access devices 130 (i.e. word lines); that the structures 174 are arranged in the z direction (third axis)).
Simsek does not explicitly teach wherein the one or more word line selectors are configured to selectively connect an output of an address decoder to a plurality of word line drivers ; and wherein the plurality of word line drivers are connected to the plurality of word lines..
Murooka teaches wherein the one or more word line selectors are configured to selectively connect an output of an address decoder to a plurality of word line drivers ; and wherein the plurality of word line drivers are connected to the plurality of word lines. (Murooka, fig 1, 2, 3, “[0044] The control circuit 17 performs an operation on the memory cell array 11 based on the control signal (and command) CNT. The control circuit 17 supplies the address ADR ( or a decoding result of the address) to the word line control circuit 12, the select gate line control circuit 13, and the global bit line control circuit 14. [0075] As shown in FIG. 3, the word line driver 121 includes a plurality of transistors DT, a plurality of global word lines GWL, and a plurality of source lines SL. [0076] A plurality of transistors (hereinafter also referred to as driver transistors) DT are arranged in an array in the circuit region of the word line driver 121. The transistors DT are in one-to-one correspondence with the word lines WL in the memory cell array 11.”; that word line drivers can drive global word lines, that individual lines are selected by transistors and address circuits to drive the one-to-one correspondence of the word lines from the peripheral circuits to the memory array).
In view of the teachings of Murooka it would have been obvious for a person of ordinary skill in the art to apply the teachings of Murooka to Simsek before the effective filing date of the claimed invention in order to teach memory circuit control. The teachings of Murooka, in the same or in a similar field of endeavor with Simsek, can combine Murooka’s more explicit peripheral section to control bit and word lines of a memory array with Simsek’s more general description of the peripheral controls. The controlling elements of both peripheral regions merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 7, Simsek, as modified by Murooka, teaches the DRAM of claim 6.
Simsek further teaches wherein if the bit lines extend along the third axis, each global bit line extends in one of the planes along the second axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction).
Regarding claim 8, Simsek, as modified by Murooka, teaches the DRAM of claim 7.
Simsek further teaches wherein each global bit line is connected to one bit line in each sub-block of the block. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction; that the local digit line is connected to a single column (i.e. sub-block) of the memory stack).
Regarding claim 9, Simsek, as modified by Murooka, teaches the DRAM of claim 7.
Simsek further teaches wherein each global bit line is connected to one bit line in each sub-block of a group of sub-blocks associated with the global bit line, and wherein different global bit lines are associated with different groups of sub-blocks. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction; that the digit lines 186A and 186B are “arranged” with different columns; that the local digit line is connected to a single column (i.e. sub-block) of the memory stack. Note: the word “associated with” can broadly be interpreted as existing in the same device on the same substrate).
Regarding claim 10, Simsek, as modified by Murooka, teaches the DRAM of claim 9.
Simsek further teaches wherein each group of sub-blocks comprises sub-blocks (14) that are arranged sequentially along the second axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction; that the digit lines 186A and 186B are “arranged” in an alternating sequences with different columns; that the local digit line is connected to a single column (i.e. sub-block) of the memory stack).
Regarding claim 11, Simsek, as modified by Murooka, teaches the DRAM of claim 9.
Simsek further teaches wherein each group of sub-blocks comprises sub-blocks that are arranged interleaved along the second axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction; that the digit lines 186A and 186B are “arranged” in an alternating, interleaved sequences with different columns; that the local digit line is connected to a single column (i.e. sub-block) of the memory stack).
Regarding claim 12, Simsek, as modified by Murooka, teaches the DRAM of claim 6.
Simsek further teaches wherein if the bit lines extend along the second axis, each global bit line extends in one of the planes along the third axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction; that the global digit lines 186A and 186B are “arranged” in different z-direction layers).
Regarding claim 13, Simsek, as modified by Murooka, teaches the DRAM of claim 12.
Simsek further teaches wherein each global bit line is connected to all bit lines in the one of the planes in each sub-block of the block. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction; that the global digit lines 186A and 186B are “arranged” in different z-direction layers; that the 186A lines are attached to a column (i.e. sub-block)).
Regarding claim 14, Simsek, as modified by Murooka, teaches the DRAM of claim 12.
Simsek further teaches wherein each global bit line is connected to a group of bit-lines in the one of the planes in each sub-block of the block, and wherein different global bit lines are associated with different groups of bit lines. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] With reference to FIG. 1M, conductive material 185 may be formed within the contact openings 184 (FIG. 1J through FIG. lL) and the trenches 181 (FIG. lJ, FIG. lK) and vertically over (e.g., in the Z-direction) surfaces of portions of the fifth insulative material 180 to form first global digit line contact structures 186A and second global digit line contact structures 186B”; that the local digit lines run in the z-direction, that the global digit lines 186A and 186B run in the y-direction; that the global digit lines 186A and 186B are “arranged” in different z-direction layers; that the 186A and 186B BLs are attached to different groups of BLs).
Regarding claim 15, Simsek, as modified by Murooka, teaches the DRAM of claim 14.
Simsek further teaches wherein each group of bit lines comprises bit lines that are arranged sequentially along the third axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] The first global digit line contact structures 186A and the second global digit line contact structures 186B are collectively referred to herein as “global digit line contact structures 186. [0099] The first global digit line contact structures 186A may have a vertical height H2 larger than a vertical height H3 of the second global digit line contact structures 186B.”; that Bit Line groups can be arranged with the Global Bit Lines arranged in the z-direction (i.e. third axis); that with only two groupings, these are arranged “sequentially” and “interleaved”).
Regarding claim 16, Simsek, as modified by Murooka, teaches the DRAM of claim 14.
Simsek further teaches wherein each group of bit lines comprises bit lines that are arranged interleaved along the third axis. (Simsek, fig 1M, 1N, 2A, 2B, “[0098] The first global digit line contact structures 186A and the second global digit line contact structures 186B are collectively referred to herein as “global digit line contact structures 186. [0099] The first global digit line contact structures 186A may have a vertical height H2 larger than a vertical height H3 of the second global digit line contact structures 186B.”; that Bit Line groups can be arranged with the Global Bit Lines arranged in the z-direction (i.e. third axis); that with only two groupings, these are arranged “sequentially” and “interleaved”).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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