Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Gadre et al., (US 8,416,251) sited in IDS filed on 05/21/2025.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As per claim 1, Gadre inherently teaches an autonomous or semi-autonomous machine (note DMA Engine, 401, Fig. 4, col. 9, lines 7-11, processing circuitry built into the memory interface, col. 2, lines 57-60) comprising: one or more graphics processing units (GPUs) (“ least one graphics processor unit (GPU) 110 and one video processor unit (VPU) 111,” Fig. 1, col. 4, lines 15-40)
one or more central processing units (CPUs) (col. 4, lines 15-35); one or more hardware accelerators (a stream based memory access system from a frame buffer memory for example GPU 110 and one video processor unit (VPU) 111,” Fig. 1, col. 4, lines 15-40), of tiles (col. 8, lines 58-64) of a frame according a frame structure (Gadre teaches a command to indicate a certain image or the like, i.e. inherently a certain data structure or the like is required from the frame buffer 205) associated with the frame (col. 7, lines 59-col. 8, lines 1-15); and one or more direct memory access (DMA) systems (note DMA Engine, 401, Fig. 4, col. 9, lines 7-11) including one or more hardware sequence (i.e. retrieval or sequential access, col. 8, lines 58-54), controllers.
As per claim 2, Gadre inherently teaches wherein the hardware sequence controller is to: receive data corresponding to one or more tiles from a source; and provide the data to a DMA engine of at least one of the DMA systems. (Gadre teaches a command to indicate a certain image or the like, i.e. inherently a certain data structure or the like is required from the frame buffer 205 associated with the frame, col., 8, lines 1 -col. 12, lines 1-32)
As per claims 3 and 4, Gadre teaches wherein the hardware sequence controller is to: receive data representative of a tile structure associated with one or more frames; and receive, from a source and based at least on the tile structure, one or more tiles associated with the one or more frames. Specifically, Gadre teaches the use of a DMA memory interface system (note DMA Engine, 401, Fig. 4, col. 9, lines 7-11) therein inherently a description identifier and further Gadre teaches the memory interface is configured to manage a plurality of streams from different originating locations and a plurality of different terminating locations. Therein, Gadre inherently teaches the 1. frame structure or the like that includes a description identifier; and 2. the tile structure or the like is retrieved based at least on a descriptor associated with the tile structure or the like corresponding to the description identifier. (col., 2, lines 28-col. 12, lines 1-32)
As per claims 5 and 6, Gadre teaches wherein the hardware sequence controller is to: receive data representative of a frame structure associated with one or more frames; and receive, from a source and based at least on the frame structure, one or more tiles associated with the one or more frames; and wherein the frame structure indicates at least one of one or more row descriptors or one or more column descriptors associated with the one or more frames.
Specifically, Gadre inherently teaches wherein:
the frame structure associated with the frame is retrieved by at least receiving a structure that includes:
a tile structure or the like associated with the frame, the tile structure indicating one or more descriptors associated with the one or more frames; and
the frame structure associated with the frame, the frame structure indicating at least one of one or more row descriptors or one or more column descriptors (Fig.6, note crossbar can access a 2x4 set of tiles from bank or another case from two adjacent banks - this inherently requires addresses to be specified in a row-column bank format, col. 10, lines 53-col. 11, lines 1-15); and
the tiles of the frame are retrieved from the source based at least on the structure.
As per claims 7 and 8, Gadre teaches wherein at least one DMA system (401, Fig. 4, col. 9, lines 7-11) of the one or more DMA systems is to: receive, using the hardware sequence controller, one or more tiles from a source; and provide the one or more tiles to at least one hardware accelerator of the one or more hardware accelerators; and wherein the one or more tiles are received using the hardware sequence controller according to a sequence; and the one or more tiles are provided to the at least one accelerator according to the sequence.
Specifically, Gadre teaches the DMA engine manages a plurality of first and second streams from different originating locations and a plurality of different terminating locations wherein each stream includes at least one prefetched tile. (Note claim 17, a second tile of one or more tiles) Further, to compensate for latency of the first or second stream the DMA engine is configured to prefetch an adjustable number of tiles therein inherently the tiles of the frame(s) are retrieved based on a certain data structure or the like required from the frame buffer 205 and the source. (col., 2, lines 28-col. 12, lines 1-32)
As per claims 9-15 and 17-20 see the rejection for claims 1-8 above.
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). 3. The following references Hung et al., (US 12,093,539) teaches DMA engine in an autonomous or semi-autonomous machine for increase performance in offloading processing tasks. (Abstract).
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/Primary Examiner, Art Unit 2184 February 7, 2026