Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1
b. Pending: 1-4
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
No IDS has been submitted.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 3, 5-6, 9 of U.S. Patent No. 12190934. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claim limitations of Instant Application is spread over claims 1-2, 3, 5-6, 9 of USP’934.
Claims 1 and 3-4 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3 of copending Application No. US 20250095709 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because both set recite same limitations over the mentioned claim ranges.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by You (US 20230128653).
Regarding independent claim 1, You discloses a memory (Figs. 1-14) comprising:
a memory core (Fig. 2 shows memory cell array 200);
a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core (Figs. 8-12 shows TABLES and [0033] describes that those TABLES store number of accesses during a row hammer monitoring time frame); and
a row hammer attack detection circuit (Fig. 3) suitable for selecting a hammered row based on a number of times that rows of the memory core are activated ([0044] describes that control logic circuit 220 may mark a row hammer address corresponding to a low access rate as a fake entry and a row hammer address corresponding to a high access rate as a real entry by using the address table including an entry identifier that distinguishes between a fake entry and a real entry. When a number of accesses corresponding to a fake entry exceeds a threshold number, the control logic circuit 220 may promote the fake entry having the number of accesses exceeding the threshold to a real entry and demote a real entry having the lowest number of accesses to a fake entry),
wherein the row hammer attack detection circuit is further suitable for giving a high weight to each of the numbers corresponding to the rows stored in the list storage circuit (Fig. 3 and [0051] describes address table 310 may be implemented as a logic circuit configured to indicate a correlation between the one or more row hammer addresses and the number of accesses of a corresponding row hammer address. The address table 310 may include registers assigned to an address storage 312 and a counter storage 314. As shown in FIG. 5, the address storage 312 and the counter storage 314 may store one or more access addresses for activating a memory cell row of the memory cell array 200 and the number of accesses. Figs. 8-12 all show column 314 basically giving a weight).
Regarding claim 4, You discloses all the elements of claim 1 as above and further rows positioned adjacent to the hammered row which is selected by the row hammer attack detection circuit are refreshed during a smart refresh operation of the memory ([0043] describes that control logic circuit 220 may be configured to identify one or more row hammer addresses corresponding to rows that are intensively accessed during a row hammer monitoring time frame, and target-refresh one or more memory cell rows physically adjacent to the one or more memory cell rows corresponding to the one or more row hammer addresses).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 20240202328).
Regarding claim 2, You discloses all the elements of claim 1 as above and further the row hammer attack detection circuit (Fig. 3) includes:
a counting circuit suitable for counting the number of times that the rows of the memory core are activated (Fig. 3 shows counter 330 and Fig. 6 along with [0064] describes a row hammer (operation S620), the control logic circuit 220 may count the number of accesses to the addresses accessed during the row hammer monitoring time frame tREFi);
a counting result storage circuit suitable for storing a counting result of the counting circuit (Fig. 3 shows counter storage 314 and [0055] describes that counter storage 314 may store the number of accesses of the fake entries and the real entries); and
a comparison circuit suitable for selecting a row with a largest counting result value among the rows stored in the counting result storage circuit as a hammered row (Fig. 3 shows comparator circuit 350 and [0058] describes that comparison circuit 350 is to identify the highest value or the lowest value of the number of accesses), and
wherein the counting circuit increases, whenever a row of the memory core is activated, a counting value of the corresponding row by +1 while increasing (Fig. 7 and [0071] describes operation S720, the control logic circuit 220 may increase a counter value of the corresponding real entry by 1),
Jung teaches whenever a row stored in the list storage circuit is activated, a counting value of the corresponding row by +X, where X is an integer equal to or greater than 2 (Fig. 12 and [0131] describes that adjacent address calculating circuit calculates one or more row-hammer addresses RH_ADD for specifying the second adjacent rows of the target row, by increasing and/or decreasing the target address TADD by two (2) (at S382)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Jung to You in order to provide a method of efficiently performing a target refresh operation as taught by Jung ([0004]).
Regarding claim 3, You and Jung together disclose all the elements of claim 2 as above and through Jung further the counting circuit samples and counts some rows among the rows that are activated in the memory core ([0037] describes counting the activation number of rows of the memory device 100 and randomly sampling rows activated in the memory device).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Jung to modified You in order to provide a method of efficiently performing a target refresh operation as taught by Jung ([0004]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 7/24/2026
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