CTNF 18/970,723 CTNF 90511 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Foreign Priority Acknowledgment is made of applicant's claim for foreign priority under 35U.S.C. 119(a)-(d). The certified copy has been placed in the file of record. Claim Objections 07-29-01 AIA Claim s 1 is objected to because of the following informalities: Claim 1 presently recites the limitation “suitable for storing data” in line 3 where claim limitation indicates memory system independently storing data. For the purpose of examination, it will be treated as “configured to store data” . Appropriate correction is required. Claim 1 presently recites the limitation “a method for operating a memory system including an interposer formed over the substrate and a plurality of memory chips stacked over the interposer” where the limitation “including” indicate memory system only has interposer formed over the substrate and a plurality of memory chips stacked over the interposer. For the purpose of examination, it will be treated as “comprising” instead of “including”. Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US Pat # 9653181) in view of Shin et al. (US Pat # 11334457) . Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Regarding independent claim 1 , Shim et al. teach a method for operating a memory system including an interposer formed over the substrate and a plurality of memory chips stacked over the interposer, suitable for storing data (see Fig. 2-4, 6, 8-10, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-67, column 22, column 23 lines 1-58, memory storing data), comprising: entering a soft repair mode; searching for available register circuits among first to N th register circuits, where N is an integer equal to or greater than 2; selecting a register circuit of a high priority among the available register circuits; and storing a failure address transferred from a memory controller into the selected register circuit (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-67, column 22, column 23 lines 1-58, Unit 1200 memory controller, step S40-S47 register searching and storing / writing). Shim et al. is silent about memory system including an interposer formed over the substrate and a plurality of memory chips stacked over the interposer. Shin et al. teach memory system including an interposer formed over the substrate and a plurality of memory chips stacked over the interposer (see Fig. 19-20, column 14, lines 54-65, column 15 lines 37-52, Substrate 940, interposer 930, stacked device 910). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Shin et al. to the teaching of Shim et al. where memory device taught by Shim et al. would be stacked as taught by Shin et al. in order to enhance performance of memory system (see column 1 lines 37-42). Further reason to combine the teachings of Shim and Shin is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards semiconductor memory array. Regarding claim 2 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends. Shim et al. further teach, further comprising setting the selected register circuit into an unavailable state (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-45). Regarding claim 3 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends. Shim et al. further teach, further comprising: receiving an undo command and an undo address transferred from the memory controller; selecting, as an undo target register circuit, a register circuit storing the same failure address as the undo address among the first to N th register circuits; and setting the undo target register circuit into an available state (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-60). Regarding claim 4 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends. Shim et al. further teach, further comprising initializing the failure address stored in the undo target register circuit (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-67, column 22, column 23 lines 1-50). Regarding claim 5 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends. Shim et al. further teach, further comprising: receiving a lock command and a lock address transferred from the memory controller; selecting, as a lock target register circuit, a register circuit storing the same failure address as the lock address among the first to N th register circuits; and setting the lock target register circuit into a locked state (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-67, column 22, column 23 lines 1-55). Regarding claim 6 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 5 on which this claim depends. Shim et al. further teach, wherein the locked state is a state in which an undo operation is impossible (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-50). Regarding claim 7 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 5 on which this claim depends. Shim et al. further teach, wherein the register circuit in the locked state is in a non-writeable state for soft repair (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-45). Regarding claim 8 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends. Shim et al. further teach, wherein the register circuit of the high priority among the available register circuits is activated in response to a high priority selection signal (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-39). Regarding independent claim 9 , Shim et al. teach an operating method of a memory in a soft repair mode, the operating method comprising: storing a failure address, which is primarily provided from a controller, in a selected register circuit having a high priority among available register circuits from plural register circuits (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-67, column 22, column 23 lines 1-58, Unit 1200 memory controller, step S40-S47 register searching and storing / writing).; and prohibiting the selected register circuit from storing subsequent data for further soft repair in response to a lock command accompanying the failure address, which is subsequently provided from the controller (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-59, column 21 lines 9-67, column 22, column 23 lines 1-58, Unit 1200 memory controller, step S40-S47 register searching and storing / writing for one specific register and prohibiting for other register). Even though Shim et al. teach command to search register but silent exclusively about lock command. Shin et al. teach lock command (see Fig. 13-14, 16, column 9 lines 13-18, column 12 lines 51-55, controller 426 locks the memory for storing). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Shin et al. to the teaching of Shim et al. where memory command taught by Shim et al. would function as taught by Shin et al. in order to enhance performance of memory system (see column 1 lines 37-42). Further reason to combine the teachings of Shim and Shin is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards semiconductor memory array. Regarding claim 10 , Shim et al. and Shin et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends. Shim et al. further teach, wherein the selected register circuit having the high priority among the available register circuits is activated in response to a high priority selection signal (see Fig. 2-4, 6, 8-11, column 3 lines 28-67, column 4, column 5 lines 1-13, column 6 lines 60-67, column 7-9, column 17 lines 65-67, column 18 lines 1-55) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment . Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824 Application/Control Number: 18/970,723 Page 2 Art Unit: 2824 Application/Control Number: 18/970,723 Page 3 Art Unit: 2824 Application/Control Number: 18/970,723 Page 4 Art Unit: 2824 Application/Control Number: 18/970,723 Page 5 Art Unit: 2824 Application/Control Number: 18/970,723 Page 6 Art Unit: 2824 Application/Control Number: 18/970,723 Page 7 Art Unit: 2824
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