Notice of Allowance
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/04/2026 has been entered.
Terminal Disclaimer
The terminal disclaimer filed on 05/11/2026 disclaiming the terminal portion of any
patent granted on this application which would extend beyond the expiration date of 12/191,852
has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11 and 21 recites “a passive inductor” but the structure of the invention in claims 8 and 19 and shown in fig. 4 does not include an inductor. Because claims 11 and 21 are depends from claim 8 and 19, the recitation of an inductor introduces a limitation that is unsupported and unclear in the context of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Forbes (US 6597203) in view of Oba et al. (JP 2015170892 A and Oba hereinafter).
Regarding claim 1, Forbes discloses a multiplexing circuit [figs. 6, 7 and 15], comprising: a first type transistor [NMOS 604, fig. 6], wherein a gate terminal [gate 604, fig. 6] of the first type transistor is configured to receive a control signal [signal A] and free from receiving a clock signal [CLK]; a second type transistor [PMOS 610, fig. 6], coupled to the first type transistor, wherein a gate terminal [gate 610] of the second type transistor is configured to receive the clock signal [CLK], and an output terminal [612], coupled between the first type transistor and the second type transistor. Forbes does not explicitly disclose an impedance circuit arranged to provide an impedance between the first type transistor and the second type transistor, wherein the impedance circuit is connected to the output terminal, wherein the impedance circuit includes a resistor, and a terminal of the resistor is connected to the gate terminal of the first type transistor while another terminal of the resistor is connected to the output terminal.
However, Oba discloses [fig. 1] an impedance circuit [124] arranged to provide an impedance [impedance of 124] between a first type transistor [PMOS 123] and a second type transistor [NMOS 121], wherein the impedance circuit is connected to an output terminal [output node between 123 and 121], the impedance circuit includes a resistor [124] and a terminal of the resistor is connected to gate terminal of the first type transistor [gate 123] while another terminal of the resistor is connected to the output terminal. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Forbes by incorporating the impedance circuit as taught in Oba in order to provide an impedance circuit to the multiplexing circuit.
Regarding claim 7, Forbes in view of Oba discloses wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Forbes in view of Oba.
Regarding claims 5 and 6, Forbes in view of Oba discloses all aspects of the instant invention with respect to claim 1 as outlined above. Forbes in view of Hissen further discloses wherein the first type transistor is a N-type Metal Oxide Semiconductor (NMOS) [604, fig. 6], a drain terminal of the NMOS is coupled to a first reference voltage [VDD], and a source terminal of the NMOS is coupled to the output terminal and wherein the second type transistor is an P-type Metal Oxide Semiconductor (PMOS) [610, fig. 6], a drain terminal of the PMOS is coupled to the output terminal, and a source terminal of the PMOS is coupled to a second reference voltage [GND]. Forbes in view of Hissen does not explicitly discloses first type transistor is a P-type Metal Oxide Semiconductor and the second type transistor is an N-type Metal Oxide Semiconductor, however, these are just different types of transistors and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Allowable Subject Matter
Claims 8-10, 12-20 and 22-23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 8 and 19, the closest prior art Kwon et al. (US 5854566) discloses an output stage of a semiconductor device [output stage of semiconductor device as shown in figs. 5-6], coupled to an output port [node 127, fig. 5] of the semiconductor device for receiving a transmission line [transmission line at node 127, fig. 5] and comprising: a multiplexing circuit [see figs. 5/6, cl. 6, ln. 46-61], comprising: a first type transistor [PMOS 123. fig. 5]; a second type transistor [NMOS 125, fig. 5], coupled to the first type transistor. Kwon does not explicitly disclose an impedance circuit, arranged to provide an impedance between the first type transistor and the second type transistor; an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled between the multiplexing circuit and the output port.
However, Hissen (US 6097253) discloses [see fig. 1] an impedance circuit [R0], arranged to provide an impedance [Ro] between first type transistor [M0] and second type transistor [M1]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Kwon by incorporate the impedance as taught in Hissen in order to provides current-mode feedback between the output and input of push-pull transistor.
Kwon in view of Hissen does not explicitly disclose wherein an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled between the output terminal and the output port.
However, Tan (US 2018/0364852) discloses [see fig. 1] wherein a driving circuit [16] coupled between the multiplexer [mux 1] output terminal and the output port [output port mux 1]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Kwon/Hissen by incorporate the driver as taught in Tan in order to provides output signal to a driving circuit. Kwon in view of Hissen further in view of Tan fails to disclose wherein an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor. This combination has been found to be non-obvious, thus allowed.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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