DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 8 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 7 and 18 of U.S. Patent No. 12191852.
Although the claims at issue are not identical, they are not patentably distinct from each other because for claim 1 of the current application, they merely omit features that is recited in the claim 1 of US Patent No. 12191852 such as “gate terminal of the first type transistor free from receiving a clock signal; the first type transistor is different from the second type transistor and wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor”; for claim 8 of the current application, they merely omit features that is recited in the claim 7 of US Patent No. 12191852 such as “wherein the first type transistor is different from the second type transistor and an impedance between a gate terminal of the first type transistor” and for claim 19 of the current application, they merely omit features that is recited in the claim 18 of US Patent No. 12191852 such as “wherein the first type transistor is different from the second type transistor and an impedance between a gate terminal of the first type transistor”. The omission of the features results in claims that are broader in scope than claims of the Patent. It would have been an obvious to one of the ordinary skill in the art to remove or not include limitation particularly where the remaining elements of the claimed invention are otherwise identical or substantially similar (see table below).
Instant application 18/97,786
US Patent No.12191852
1. A multiplexing circuit, comprising: a first type transistor, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal;
a second type transistor, coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal;
and an impedance circuit arranged to provide an impedance between the first type transistor and the second type transistor.
1. A multiplexing circuit, comprising: a first type transistor, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal;
a second type transistor, coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; and an impedance circuit arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.
8. An output stage of a semiconductor device, coupled to an output port of the semiconductor device for receiving a transmission line and comprising: a multiplexing circuit, comprising: a first type transistor; a second type transistor, coupled to the first type transistor; and an impedance circuit, arranged to provide an impedance between the first type transistor and the second type transistor; an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled between the multiplexing circuit and the output port.
7. An output stage of a semiconductor device, coupled to an output port of the semiconductor device for receiving a transmission line and comprising: a multiplexing circuit, comprising: a first type transistor; a second type transistor, coupled to the first type transistor, wherein the first type transistor is different from the second type transistor; and an impedance circuit, arranged to provide an impedance between a gate terminal of the first type transistor and the second type transistor; an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled between the multiplexing circuit and the output port.
19. A semiconductor device, comprising: an output stage, including: a multiplexing circuit, including: a first type transistor; a second type transistor, coupled to the first type transistor; and an impedance circuit, arranged to provide an impedance between the first type transistor and the second type transistor; an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled to the multiplexing circuit; and an output port, coupled to the driving circuit and configured to receive a transmission line.
18. A semiconductor device, comprising: an output stage, including: a multiplexing circuit, including: a first type transistor; a second type transistor, coupled to the first type transistor, wherein the first type transistor is different from the second type transistor; and an impedance circuit, arranged to provide an impedance between a gate terminal of the first type transistor and the second type transistor; an input circuit arranged to receive a first clock signal and a second clock signal, including a sub-output terminal, and the sub-output terminal is connected to a gate terminal of the second type transistor; and a driving circuit, coupled to the multiplexing circuit; and an output port, coupled to the driving circuit and configured to receive a transmission line.
Claims 2-6, 9-18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-6, 8-17 and 19 of U.S. Patent No. 12191852.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Forbes (US 6597203) in view of in view of Raman et al. (US 6424170 and Raman hereinafter).
Regarding claim 1, Forbes discloses a multiplexing circuit [figs. 6, 7 and 15], comprising: a first type transistor [604, fig. 6], wherein a gate terminal [gate 604, fig. 6] of the first type transistor is configured to receive a control signal [signal A] and free from receiving a clock signal [CLK]; a second type transistor [610, fig. 6], coupled to the first type transistor, wherein a gate terminal [gate 610] of the second type transistor is configured to receive the clock signal [CLK]. Forbes does not disclose an impedance circuit arranged to provide an impedance between the first type transistor and the second type transistor.
However, Raman discloses [figs. 1 and 3] an impedance circuit [LRB, fig. 3] arranged to provide an impedance between a first type transistor [30, fig. 3] and a second type transistor [20, fig. 1]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Forbes by incorporating the impedance circuit as taught in Raman in order to provides matching termination that suppresses overshoots and residual noises, and also improves signal quality, timing, and device reliability [cl. 3~cl. 4].
Regarding claim 2, Forbes in view of Raman discloses [fig. 6]: an output terminal [612], coupled between the first type transistor and the second type transistor, wherein the impedance circuit is connected to the output terminal.
Regarding claim 7, Forbes in view of Raman discloses [fig. 6] wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Forbes in view of in view of Raman et al.
Regarding claim 5, Forbes in view of Raman discloses all the features with respect to claim 2 as indicated above. Forbes in view of Raman further discloses [fig. 6] wherein the first type transistor is a N-type Metal Oxide Semiconductor [604], a drain terminal of the NMOS is coupled to a first reference voltage [ground], and a source terminal of the NMOS is coupled to the output terminal. Forbes in view of Raman does not explicitly disclose the first type transistor is a P-type Metal Oxide Semiconductor. Although Forbes in view of Raman discloses uses N-type MOSFETs instead of P-type Metal Oxide Semiconductor for the first transistor, the transistor is just different type of transistor and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Regarding claim 6, Forbes in view of Raman discloses all the features with respect to claim 2 as indicated above. Forbes in view of Raman further discloses [fig. 6] wherein the second type transistor is P-type Metal Oxide Semiconductor (PMOS) [610], a drain terminal of the NMOS is coupled to the output terminal, and a source terminal of the NMOS is coupled to a second reference voltage [VDD]. Forbes in view of Raman does not explicitly disclose the second type transistor is N-type Metal Oxide Semiconductor. Although Forbes in view of Raman discloses uses P-type MOSFETs instead of N-type Metal Oxide Semiconductor for the second transistor, the transistor is just different type of transistor and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842