Prosecution Insights
Last updated: July 17, 2026
Application No. 18/970,786

MULTIPLEXING CIRCUIT, OUTPUT STAGE, AND SEMICONDUCTOR DEVICE

Final Rejection §103§112
Filed
Dec 05, 2024
Priority
Aug 30, 2021 — continuation of 11/575,378 +2 more
Examiner
RETEBO, METASEBIA T
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
585 granted / 655 resolved
+21.3% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
26 currently pending
Career history
679
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
70.3%
+30.3% vs TC avg
§102
17.4%
-22.6% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 655 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Terminal Disclaimer The terminal disclaimer filed on 05/11/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 12/191,852 has been reviewed and is accepted. The terminal disclaimer has been recorded. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-3, 5-7 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1, 11 and 21 recite “the multiplexing circuit is free from coupling a passive inductor to the output terminal of the multiplexing circuit.” It is unclear how the multiplexing circuit is free from coupling a passive inductor to the output terminal of the multiplexing circuit. The applicant drawing figure 2 shows that the multiplexing circuit is coupling [through R1] a passive inductor [L1] to the output terminal of the multiplexing circuit [OUT]. Claims 2-3 and 5-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claim 1. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Forbes (US 6597203) in view of in view of Raman et al. (US 6424170 and Raman hereinafter). Regarding claim 1, Forbes discloses a multiplexing circuit [figs. 6, 7 and 15], comprising: a first type transistor [604, fig. 6], wherein a gate terminal [gate 604, fig. 6] of the first type transistor is configured to receive a control signal [signal A] and free from receiving a clock signal [CLK]; a second type transistor [610, fig. 6], coupled to the first type transistor, wherein a gate terminal [gate 610] of the second type transistor is configured to receive the clock signal [CLK], and an output terminal [612], coupled between the first type transistor and the second type transistor; wherein the multiplexing circuit is free from coupling a passive inductor to the output terminal of the multiplexing circuit [Examiner noted that a passive inductor not required as claim limitation because multiplexing circuit is free from coupling a passive inductor to the output terminal of the multiplexing circuit and a passive inductor is not recited anywhere else in the claim and is not structurally connected to any other claimed element.]. Forbes does not disclose an impedance circuit arranged to provide an impedance between the first type transistor and the second type transistor. However, Raman discloses [figs. 1 and 3] an impedance circuit [LRB, fig. 3] arranged to provide an impedance between a first type transistor [30, fig. 3] and a second type transistor [20, fig. 1]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Forbes by incorporating the impedance circuit as taught in Raman in order to provides matching termination that suppresses overshoots and residual noises, and also improves signal quality, timing, and device reliability [cl. 3~cl. 4]. Regarding claim 2, Forbes in view of Raman discloses [fig. 6] wherein the impedance circuit is connected to the output terminal [fig. 3]. Regarding claim 7, Forbes in view of Raman discloses [fig. 6] wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Forbes in view of in view of Raman et al. Regarding claim 5, Forbes in view of Raman discloses all the features with respect to claim 2 as indicated above. Forbes in view of Raman further discloses [fig. 6] wherein the first type transistor is a N-type Metal Oxide Semiconductor [604], a drain terminal of the NMOS is coupled to a first reference voltage [ground], and a source terminal of the NMOS is coupled to the output terminal. Forbes in view of Raman does not explicitly disclose the first type transistor is a P-type Metal Oxide Semiconductor. Although Forbes in view of Raman discloses uses N-type MOSFETs instead of P-type Metal Oxide Semiconductor for the first transistor, the transistor is just different type of transistor and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art. Regarding claim 6, Forbes in view of Raman discloses all the features with respect to claim 2 as indicated above. Forbes in view of Raman further discloses [fig. 6] wherein the second type transistor is P-type Metal Oxide Semiconductor (PMOS) [610], a drain terminal of the NMOS is coupled to the output terminal, and a source terminal of the NMOS is coupled to a second reference voltage [VDD]. Forbes in view of Raman does not explicitly disclose the second type transistor is N-type Metal Oxide Semiconductor. Although Forbes in view of Raman discloses uses P-type MOSFETs instead of N-type Metal Oxide Semiconductor for the second transistor, the transistor is just different type of transistor and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art. Response to Arguments Applicant's arguments filed 05/11/2026 have been fully considered but they are not persuasive. Regarding claim 1, the amended feature “and an output terminal, coupled between the first type transistor and the second type transistor”. Forbes discloses an output terminal [612, fig. 6], coupled between the first type transistor [604, fig. 6] and the second type transistor [610, fig. 6]. And for the amended limitation “wherein the multiplexing circuit is free from coupling a passive inductor to the output terminal of the multiplexing circuit”. Examiner noted that a passive inductor is not required as claim limitation because the claim recites multiplexing circuit is free from coupling a passive inductor to the output terminal of the multiplexing circuit and a passive inductor is not recited anywhere else in the claim and is not structurally connected to any other claimed element. Accordingly, since the cited reference does not include passive inductor and therefore free from any coupling to the output of multiplexing circuit. Therefore, Forbes/Raman still read on the claims and the rejection stands. Allowable Subject Matter Claims 8-10 and 12-20 are allowed. Claims 3, 11 and 21 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Dec 05, 2024
Application Filed
Feb 19, 2026
Non-Final Rejection mailed — §103, §112
May 11, 2026
Response Filed
May 28, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+5.4%)
1y 10m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 655 resolved cases by this examiner. Grant probability derived from career allowance rate.

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