Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1
b. Pending: 1-4
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
No information disclosure statement has been filed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 and 9 of U.S. Patent No. US 12190934. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claim limitations of instant application is basically spread over claims 1-7 and 9 of USP’934.
Claims 1-4 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of copending Application No. 18/970,705 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because both set recite same claim limitations over the above mentioned ranges.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20220270669) in view of Morohashi et al. (US 11152050).
Regarding independent claim 1, Fan discloses a memory (Figs. 1-3) comprising:
a memory core (Fig. 1 and [0019] describes memory array 16);
a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core (Fig. 1 and [0015] describes logical arithmetic unit 14, connected to an output terminal of seed arithmetic unit 13 and configured to obtain a row hammer refresh address 141 according to the seed address 132, the row hammer refresh address 141 is an adjacent physical address of the seed address 132. Each of the seed arithmetic unit and the logical arithmetic unit may include an arithmetic and logic unit, an accumulator and registers. Here registers are suitable for storing row hammered list);
a sampling circuit suitable for sampling and storing a portion of active addresses used for active operations of the memory core and increasing a sampling probability of an active address corresponding to the rows stored in the list storage circuit among the active addresses; and
a selection circuit suitable for selecting one among the sampled addresses stored in the sampling circuit as a hammered row address in a predetermined order whenever a smart refresh operation is performed (Fig. 1 and [0015] describes a refresh signal 131 as an excitation signal and a pre-decode unit 15, connected to an output terminal of the logical arithmetic unit 14 and configured to receive the row hammer refresh address 141, and convert the row hammer refresh address 141 into a physical address to be used by a memory array of a memory to perform a refresh operation. [0038] and [0042] describes that logical arithmetic unit 14 determines, by default, a +1 physical address and a −1 physical address that are adjacent to the seed address 132 as the row hammer refresh addresses 141, or defaults the +1 physical address, the −1 physical address, a +2 physical address, and a −2 physical address as the row hammer refresh addresses 141. Also, the preset number of times at least includes a first preset number of times and a second present number of times, when the cumulative number of accesses is greater than the first preset number of times but less than the second preset number of times, the row hammer refresh addresses are the +1 physical address and the −1 physical address adjacent to the seed address, when the cumulative number of accesses is greater than or equal to the second preset number of times, the row hammer refresh addresses are the +2 physical address, the +1 physical address, the −1 physical address, and the −2 physical address adjacent to the seed address. That is to say, compared with the seed address 132, an adjacent range of the row hammer refresh address 141 may be adjusted according to the cumulative number of accesses to ensure that the adjacent word line influenced by the row hammer effect may be refreshed timely. These are various predetermined schemes that ).
Fan does not explicitly show a sampling circuit suitable for sampling and storing a portion of active addresses used for active operations of the memory core and increasing a sampling probability of an active address corresponding to the rows stored in the list storage circuit among the active addresses;
However, Morohashi teaches a sampling circuit suitable for sampling and storing a portion of active addresses used for active operations of the memory core and increasing a sampling probability of an active address corresponding to the rows stored in the list storage circuit among the active addresses (Fig. 1 and (23) describes that refresh address control circuit may sample the current row address XADD to determine its characteristics over time. The sampling may occur intermittently, with each sample acquired based on a random or pseudo-random timing. The refresh address control circuit 40 may use different methods to calculate a hammer refresh address based on the sampled row address XADD. Fig. 3 and (31)-(32) elaborates the same concept of sample circuit 341);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Morohashi to Fan in order to provide methods to mitigate row hammer effects by refreshing victim rows which are adjacent or not to the aggressor row as taught by Morohashi (9).
Regarding claim 2, Fan and Morohashi together disclose all the elements of claim 1 as above and through Morohashi further the sampling circuit (Figs. 4-5) includes:
a first random pulse generator suitable for generating a first random pulse; a second random pulse generator suitable for generating a second random pulse that is activated more frequently than the first random pulse (Fig. 5 and (57) describes second refresh cycle generator 500 may generate the second command signal RHRplusEn in response to a number of activations of the first command signal Rhr. The second command signal RHRplusEn in combination with the first command signal Rhr may indicate that a second refresh operation is to take place, different than the refresh operation which is indicated by the first command signal Rhr alone. The first and second command signals may be produced at different rates. The rates at which the first and second command signals are produced may be determined based on the row hammer refresh operation they indicate. As an example, the first command signal Rhr may refresh a row which is adjacent to an identified row hammer and the second command signal RHRplusEn may refresh a row which is non-adjacent to the identified row hammer. In this situation, the adjacent rows may be expected to be more affected by a row hammer effect than the non-adjacent rows, and so Rhr may be produced more frequently than RHRplusEn); and
a register circuit suitable for sampling and storing the row address when an active signal is activated in an activation period of the first random pulse and a row address does not correspond to one among the rows stored in the list storage circuit, and sampling and storing the row address when the active signal is activated in an activation period of the second random pulse and when the row address corresponds to one among the rows stored in the list storage circuit (Fig. 6 and (66)-(67) describes row hammer refresh address HitXADD2. The hammer refresh address HitXADD2 is calculated in response to the first and second command signals Rhr, RHRplusEn based on the currently provided row hammer address HitXADD1. As shown, a row hammer refresh address is calculated for row hammer address ‘A’ when the first command signal Rhr is activated. Since only the first but not second command signals are activated at this point, a first refresh operation is carried out in which adjacent rows to the row corresponding to address A are refreshed, and A+/−1 is output as the hammer refresh address HitXADD2. An address corresponding to A+1 may be output during the refresh signal AREF pulse labeled “1.sup.st RHR”, and an address corresponding to A−1 may be output during the refresh pulse labeled “2.sup.nd RHR”. When both the first and second command signals activate, the address C is the row hammer address HitXADD1, and a second refresh operation causes C+/−2 to be provided as the hammer refresh address HitXADD2. An address corresponding to C+2 may be output during the refresh signal AREF pulse labeled “1.sup.st RHR”, and an address corresponding to C−2 may be output during the pulse labeled “2.sup.nd RHR”. The irregular timing of the first sampling signal S1 means that addresses A and C each have different refresh operations calculated, and address B has none. Various patterns and sequences of address refreshes may be provided based on the operation of the address refresh circuit).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Morohashi to modified Fan in order to provide methods to mitigate row hammer effects by refreshing victim rows which are adjacent or not to the aggressor row as taught by Morohashi (9).
Regarding claim 3, Fan and Morohashi together disclose all the elements of claim 1 as above and through Fan further rows positioned adjacent to the hammered row which is selected by the selection circuit are refreshed during a smart refresh operation of the memory (Fig. 2 and [0044] describes the refresh circuit may send the physical addresses corresponding to the base address N−1 and the base N+1 in the refresh phase to the memory array 16 for the memory array 16 to perform the refresh operation).
Regarding claim 4, Fan and Morohashi together disclose all the elements of claim 1 as above and through Morohashi further the sampling circuit (Fig. 3) includes:
a random pulse generator suitable for generating a random pulse signal (Fig. 3 and (44) describes cycle generator 348 periodically outputs a first command signal Rhr or a second command signal RHRplusEn); and
a register circuit suitable for sampling and storing a row address which is used for an active operation based on the random pulse signal (Fig. 3 and (45) describes refresh address generator 347 that updates the current automatic refresh address Pre_RXADD to a next address),
wherein the register circuit samples the row address once whenever the random pulse signal pulses X times, where X is an integer equal to or greater than 1, when the row address corresponds to one among the rows stored in the list storage circuit, and samples the row address once whenever the random pulse signal pulses Y times, where Y>X, and Y is an integer greater than X, when the row address does not correspond to one among the rows stored in the list storage circuit (Fig. 6 and (66)-(67)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Morohashi to modified Fan in order to provide methods to mitigate row hammer effects by refreshing victim rows which are adjacent or not to the aggressor row as taught by Morohashi (9).
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 8/13/2026
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