DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 6 and 7 have been amended.
Claims 1-15 have been examined.
The drawing objections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Drawings
The drawings are objected to because of the following informalities.
The sheet numbering is improperly formatted. The figures therefore fail to comply with 37 CFR 1.84(t), which states, “The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking.” The sheet numbering is too small and includes extraneous text. The sheet numbering should be, e.g., 1/4, with no other text.
In Figure 2, the text, “Computing area 3” is mingled with the lines. The figures therefore fail to comply with 37 CFR 1.84(p)(3), which states, “Numbers, letters, and reference characters …should not cross or mingle with the lines.”
In Figures 1-4, lines are faint, fuzzy, blurry, and pixelated. The figures therefore fail to comply with 37 CFR 1.84(p)(3), which states, “All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views.” This is often the result of using grayscale or dithering in printing.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2023/0281156 by Zhang et al. (hereinafter referred to as “Zhang”).
Regarding claim 1, Zhang discloses:
a reconfigurable processor chip, comprising: a plurality of reconfigurable processing elements based on distributed storage, components of the reconfigurable processing elements being logically interconnected, wherein the components comprise (Zhang discloses, at Figure 1C and related description, a reconfigurable data processor that includes an array of configurable units. As disclosed at ¶ [0049], the processor uses distributed memory. As shown at Figure 3A, components of the configurable units are logically interconnected.):
a reconfigurable computing component configured to calculate data (Zhang discloses, at Figure 4 and related description, a pattern compute unit, which discloses a reconfigurable computing component configured to calculate data.);
a data flow controller using a data flow driving mode, the data flow driving mode is configured to control start and end of a computing task and a data transmission task based on data flow information about the computing task and message transferring of upstream and downstream reconfigurable processing elements (Zhang discloses, at Figure 4 and related description, a control block that controls starting and ending processing. See, e.g., ¶ [0085]. Zhang also discloses, at Figure 4 and related description, transmitting data. The starting, ending, and data transmission with adjacent units are understood to be based on data flow information about computing tasks. See, e.g., ¶ [0102].);
a distributed memory configured to implement data storage of a corresponding reconfigurable processing element (Zhang discloses, at Figure 5 and related description, pattern memory units, which discloses a distributed memory configured to implement data storage of a corresponding reconfigurable processing element.); and
a programmable data routing element configured to implement communication between the plurality of reconfigurable processing elements to control a direction of a data packet, and implement flexible transmission of the data packet (Zhang discloses, at Figure 3B and related description, switches that link the configurable units, which discloses a programmable data routing element configured to implement communication between the plurality of reconfigurable processing elements to control a direction of a data packet, and implement flexible transmission of the data packet.).
Regarding claim 2, Zhang discloses the elements of claim 1, as discussed above. Zhang also discloses:
the programmable data routing element is configured to change a routing direction and a routing destination of the data packet in real time by software configuration using a software programmable routing policy (Zhang discloses, at Figure 3B and related description, switches that link the configurable units and can transmit data during operation, which discloses the programmable data routing element is configured to change a routing direction and a routing destination of the data packet in real time by software configuration using a software programmable routing policy.).
Regarding claim 3, Zhang discloses the elements of claim 1, as discussed above. Zhang also discloses:
the reconfigurable processing element is configured to exchange data over a network-on-chip, an inter-chip interface and a network cable within a storage capacity range of a storage space (Zhang discloses, at ¶ [0047] et seq., an array level network (ALN), which discloses exchanging data over a network on chip. Zhang also discloses, at ¶ [0083], sending requests off-chip, which discloses an inter-chip interface as off-chip memory is understood to be implemented using chips. Zhang also discloses, at ¶ [0048], the ALN uses wires to transmit information, which discloses a network cable within a storage capacity range of a storage space.).
Regarding claim 4, Zhang discloses the elements of claim 1, as discussed above. Zhang also discloses:
the plurality of reconfigurable processing elements are divided into a plurality of computing areas based on algorithmic mapping requirements (Zhang discloses, at Figure 1A and related description, dividing the processing elements based on the algorithm to be performed. See also Figure 7 and related description, which discloses partitioning code and corresponding assignment of resources.),
wherein a communication connection relationship of the programmable data routing element is changed in real time by changing configuration of an execution graph in the reconfigurable processing elements in the data flow driving mode of the data flow controller, and a division of the computing areas is changed based on the communication connection relationship (Zhang discloses, at Figure 7 and related description, runtime determination of placement and routing for assigning a physical dataflow graph to processing and memory resources, which discloses a communication connection relationship of the programmable data routing element is changed in real time by changing configuration of an execution graph in the reconfigurable processing elements in the data flow driving mode of the data flow controller, and a division of the computing areas is changed based on the communication connection relationship.).
Regarding claim 5, Zhang discloses the elements of claim 4, as discussed above. Zhang also discloses:
the plurality of computing areas perform pipeline computing or perform different assigned computing tasks (Zhang discloses, at ¶ [0035], performing pipelined processing.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of US Publication No. 2010/0158023 by Mukhopadhyay et al. (hereinafter referred to as “Mukhopadhyay”).
Regarding claim 6, Zhang discloses:
a reconfigurable processor cluster, comprising: a plurality of reconfigurable processor…[tiles], wherein a reconfigurable processor chip of the plurality of reconfigurable processor chips is composed of a plurality of reconfigurable processing elements based on distributed storage, and components of the reconfigurable processing elements are logically interconnected and comprise (Zhang discloses at Figure 2, a plurality of tiles each having an array of configurable units. Zhang discloses, at Figure 1C and related description, a reconfigurable data processor that includes an array of configurable units. As disclosed at ¶ [0049], the processor uses distributed memory. As shown at Figure 3A, components of the configurable units are logically interconnected.):
a reconfigurable computing component configured to calculate data (Zhang discloses, at Figure 4 and related description, a pattern compute unit, which discloses a reconfigurable computing component configured to calculate data.);
a data flow controller using a data flow driving mode, the data flow driving mode is configured to control start and end of a computing task and a data transmission task based on data flow information about the computing task and message transferring of upstream and downstream reconfigurable processing elements (Zhang discloses, at Figure 4 and related description, a control block that controls starting and ending processing. See, e.g., ¶ [0085]. Zhang also discloses, at Figure 4 and related description, transmitting data. The starting, ending, and data transmission with adjacent units are understood to be based on data flow information about computing tasks. See, e.g., ¶ [0102].);
a distributed memory configured to implement data storage of a corresponding reconfigurable processing element; (Zhang discloses, at Figure 5 and related description, pattern memory units, which discloses a distributed memory configured to implement data storage of a corresponding reconfigurable processing element.); and
a programmable data routing element configured to implement communication between the plurality of reconfigurable processing elements to control a direction of a data packet, and implement flexible transmission of the data packet (Zhang discloses, at Figure 3B and related description, switches that link the configurable units, which discloses a programmable data routing element configured to implement communication between the plurality of reconfigurable processing elements to control a direction of a data packet, and implement flexible transmission of the data packet.).
Zhang does not explicitly disclose the aforementioned tiles are implemented using a plurality of chips.
However, in the same field of endeavor (e.g., parallel processing) Mukhopadhyay discloses:
multi-chip modules (Mukhopadhyay discloses, at the Abstract, multi-chip modules.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang to implement the plurality of tiles using a plurality of chips, as disclosed by Mukhopadhyay, because whether to implement a plurality of components on one chip or on separate chips is an obvious design choice that would be determined based on circumstances, each option having well-known benefits and drawbacks.
Regarding claim 7, Zhang, as modified, discloses the elements of claim 6, as discussed above. Zhang also discloses:
a routing control module is configured to implement data communication among the plurality of reconfigurable processor…[tiles] (Zhang discloses, at Figure 2, the tiles are communicatively coupled via top level switches, which discloses a routing control module.),
wherein a reconfigurable processing element among the plurality of reconfigurable processing elements of the plurality of reconfigurable processor …[tiles] is configured to perform the data communication via a network by the programmable data routing element and the routing control module, and the programmable data routing element and the routing control module on the reconfigurable processor chip are connected by the network on the reconfigurable processor chip (Zhang discloses, at ¶ [0047] et seq., an array level network (ALN), which discloses the reconfigurable processing element among the plurality of reconfigurable processor …[tiles] is configured to perform the data communication via a network by the programmable data routing element and the routing control module, and the programmable data routing element and the routing control module on the reconfigurable processor chip are connected by the network on the reconfigurable processor chip.); and
the routing control module is configured to receive or send a network data packet among the reconfigurable processor …[tiles] (Zhang discloses.
Zhang does not explicitly disclose the aforementioned tiles are implemented using a plurality of chips.
However, in the same field of endeavor (e.g., parallel processing) Mukhopadhyay discloses:
multi-chip modules (Mukhopadhyay discloses, at the Abstract, multi-chip modules.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang to implement the plurality of tiles using a plurality of chips, as disclosed by Mukhopadhyay, because whether to implement a plurality of components on one chip or on separate chips is an obvious design choice that would be determined based on circumstances, each option having well-known benefits and drawbacks.
Regarding claim 8, Zhang, as modified, discloses the elements of claim 7, as discussed above. Zhang also discloses:
the routing control module has a bidirectional …function to send read request, write request, read response and write response control information (Zhang discloses, at Figure 2 and related description, sending data between the tiles, which discloses bidirectional functionality. Zhang also discloses, at ¶ [0047] et seq., an array level network (ALN), which discloses send read request, write request, read response and write response control information.).
Zhang does not explicitly disclose Ethernet data transceiving and a flow control mechanism, and has functions of sending buffer back pressure and receiving buffer back pressure to control data transmission at a receiving end and a sending end.
However, in the same field of endeavor (e.g., parallel processing) Mukhopadhyay discloses:
bidirectional Ethernet ports (Mukhopadhyay discloses, at ¶ [0049], bidirectional Ethernet ports.); and
back pressure flow control messages (Mukhopadhyay discloses, at ¶ [0087], back-pressure flow control messages.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang to include Ethernet and back-pressure flow control, as disclosed by Mukhopadhyay in order to improve performance by providing stable communication capabilities.
Regarding claim 9, Zhang, as modified, discloses the elements of claim 6, as discussed above. Zhang also discloses:
the plurality of reconfigurable processing elements on the reconfigurable processor chip are divided into a plurality of computing areas based on algorithm mapping requirements (Zhang discloses, at Figure 1A and related description, dividing the processing elements based on the algorithm to be performed. See also Figure 7 and related description, which discloses partitioning code and corresponding assignment of resources.); and
the reconfigurable processor cluster is configured to support flexible division of the computing areas, and support asynchronous parallel computing on the computing areas (Zhang discloses, at ¶ [0034], reconfigurable units, which discloses flexible division of the computing areas, that support dataflow computing, which discloses asynchronous parallel computing.).
Regarding claim 10, Zhang, as modified, discloses the elements of claim 6, as discussed above. Zhang also discloses:
the reconfigurable processor cluster is configured to support a plurality of computing modes, a data parallel computing mode, a pipeline parallel computing mode or a model parallel computing mode (Zhang disclsoses, at ¶ [0035], supporting both parallel and pipelined modes.).
Regarding claim 11, Zhang, as modified, discloses the elements of claim 6, as discussed above. Zhang also discloses:
resources of the reconfigurable processor cluster are allocated to a plurality of tasks for parallel computing (Zhang discloses, at Figure 1A and related description, dividing the processing elements based on the algorithm to be performed. See also Figure 7 and related description, which discloses partitioning code and corresponding assignment of resources.).
Regarding claim 12, Zhang, as modified, discloses the elements of claim 6, as discussed above. Zhang also discloses:
the programmable data routing element is configured to change a routing direction and a routing destination of the data packet in real time by software configuration using a software programmable routing policy (Zhang discloses, at Figure 3B and related description, switches that link the configurable units and can transmit data during operation, which discloses the programmable data routing element is configured to change a routing direction and a routing destination of the data packet in real time by software configuration using a software programmable routing policy.).
Regarding claim 13, Zhang, as modified, discloses the elements of claim 6, as discussed above. Zhang also discloses:
the reconfigurable processing element is configured to exchange data over a network-on-chip, an inter-chip interface and a network cable within a storage capacity range of a storage space (Zhang discloses, at ¶ [0047] et seq., an array level network (ALN), which discloses exchanging data over a network on chip. Zhang also discloses, at ¶ [0083], sending requests off-chip, which discloses an inter-chip interface as off-chip memory is understood to be implemented using chips. Zhang also discloses, at ¶ [0048], the ALN uses wires to transmit information, which discloses a network cable within a storage capacity range of a storage space.).
Regarding claim 14, Zhang, as modified, discloses the elements of claim 6, as discussed above. Zhang also discloses:
the plurality of reconfigurable processing elements are divided into a plurality of computing areas based on algorithmic mapping requirements (Zhang discloses, at Figure 1A and related description, dividing the processing elements based on the algorithm to be performed. See also Figure 7 and related description, which discloses partitioning code and corresponding assignment of resources.),
wherein a communication connection relationship of the programmable data routing element is changed in real time by changing configuration of an execution graph in the reconfigurable processing elements in the data flow driving mode of the data flow controller, and a division of the computing areas is changed based on the communication connection relationship (Zhang discloses, at Figure 7 and related description, runtime determination of placement and routing for assigning a physical dataflow graph to processing and memory resources, which discloses a communication connection relationship of the programmable data routing element is changed in real time by changing configuration of an execution graph in the reconfigurable processing elements in the data flow driving mode of the data flow controller, and a division of the computing areas is changed based on the communication connection relationship.).
Regarding claim 15, Zhang, as modified, discloses the elements of claim 14, as discussed above. Zhang also discloses:
the plurality of computing areas perform pipeline computing or perform different assigned computing tasks (Zhang discloses, at ¶ [0035], performing pipelined processing.).
Response to Arguments
On pages 7-8 of the response filed May 15, 2026 (“response”), the Applicant argues, “Zhang's "control block 470" is a generic hardware interface for physical control signals - specifically, signals indicating the start or end of execution of a configurable unit. However, in the present application, the reconfigurable processing element (RPE) uses the data flow driving computing mode to control the start and end of the computing task based on the data flow information about the computing task and message transferring of the upstream and downstream RPEs, thus achieving asynchronous parallel computing of each computing element (see, e.g., paragraphs [0049] and [0075] of the specification of the present application as originally filed). Zhang contains no disclosure that the "control block 470" receives, parses, or acts upon messages communicated between processing elements. In Zhang, inter-unit messages are payload to be processed, not control signals that trigger "control block" to start or end a computing task (see, e.g., paragraphs [0071]-[0087] of Zhang). Thus, Zhang fails to disclose a data flow controller that acts based on "data flow information about the computing task" and "message transferring of the upstream and downstream RPEs" as required by claim 1.”
Though fully considered, the Examiner respectfully disagrees. Zhang explicitly discloses transmitting control inputs and outputs between upstream and downstream processing elements. See, e.g., ¶ [0085]. The Examiner maintains that these control signals disclose control starting and ending of computing and transmission tasks. In the context of dataflow computing, what else would they be? That is, in dataflow computing, tasks are started at consumer nodes based on detecting completion of tasks by producer nodes. Thus, communication between upstream and downstream nodes of control inputs that control starting and ending of tasks, as disclosed by Zhang, is integral in dataflow computing. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 8 of the response the Applicant argues, “Further, paragraph [0102] of Zhang discloses a data processing method 700 that includes the steps of receiving (710) dataflow operations for a reconfigurable computing system, partitioning (720) the dataflow operations into selected executable partitions, assigning (730) selected executable partitions to reconfigurable units, configuring (740) the reconfigurable units, and processing (750) data with the reconfigurable units. In Zhang, all data flow analysis, task partitioning, and resource assignment decisions are made during the compilation/configuration phases, prior to task execution. Once configuration is complete, processing units execute according to the configuration. There is no data flow controller starting and ending a computing task and a data transmission task based on data flow information about the computing task and message transferring of upstream and downstream reconfigurable processing elements as recited in claim 1 of the present application. Zhang addresses the challenge that "partitioning dataflow operations and assigning the partitioned operations to available processing resources" presents, by optimizing the compiler to perform these tasks at compile time (see, e.g., paragraph [0012] of Zhang). Zhang thus teaches that control logic should be resolved before execution. Those skilled in the art, following Zhang's express teachings, would be directed toward improving the compiler, not toward restructuring the architecture to implement a data flow controller as recited in claim 1 of the present application. Therefore, Zhang does not teach and/or suggest the above feature (a) as set forth in claim 1 of the present application.”
Though fully considered, the Examiner respectfully disagrees. While the computing tasks may be partitioned and assigned during compilation, at run time, a given node does not begin performing its assigned task until the node’s neighboring nodes have signaled to the node their readiness. For example, ¶ [0051] of Zhang discloses a producer releasing data only when the producer determines that the consumer is ready for it. In dataflow computing, the ascertaining is done using control signals exchanged between the nodes, rather than a fixed length clock. Similarly, a consumer node waits to start its processing task until it receives an indication form a consumer node that its needed input data is ready. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 9 of the response the Applicant argues, “As set forth in this application, "flexible transmission" recited in claim 1 is a transmission capable of being dynamically adapted during runtime - for example, to bypass a corrupted processing element (see e.g., paragraph [0049] of the specification of the present application as originally filed). On the other hand, paragraph [0077] of Zhang reads that: "FIG. 3 B illustrates an example switch unit connecting elements in an ALN. As shown in the example of FIG. 3 B, a switch unit can have 8 interfaces. The North, South, East and West interfaces of a switch unit are used for connections between switch units. The Northeast, Southeast, Northwest and Southwest interfaces of a switch unit are each used to make connections to PCU or PMU instances..." (emphasis added) Zhang's switch unit, while configurable, is configured as part of the bitstream during the compilation phase. Its routing behavior is fixed during the "processing" phase. Zhang does not mention a routing element whose transmissions can be flexibly changed in real time during task execution at all. Therefore, Zhang does not teach and/or suggest feature (b) as set forth in claim 1 of the present application.”
Though fully considered, the Examiner respectfully disagrees. The applicant is arguing limitations not present in the claims. For example, the claims do not recited dynamically adapting a route during runtime to bypass a corrupted processing element. Zhang’s disclosure of routing elements that can be reconfigured to control a direction discloses the claimed flexible transmission. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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