DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 11, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kojima Publication No. US 2009/0284885.
Regarding claim 1, Kojima discloses a semiconductor device comprising:
a high-electron mobility transistor [Fig. 3, transistor M102];
a short-circuit detection circuit [Fig. 3, comprising M103 and Rs120] configured to output a short-circuit protection voltage [Fig. 3, Rs120 converts a sense current Isense of the M103 into a sense voltage; par. 0007] based on a gate voltage of the high-electron mobility transistor and a drain voltage of the high-electron mobility transistor [Fig. 3, the drain of the sense MOS transistor 103 is connected to the drain of the main transistor M102 and the gate of the sense MOS transistor is connected o the gate of the main transistor M102 as shown]; and
a protection circuit configured to reduce the gate voltage of the high-electron mobility transistor based on the short-circuit protection voltage [par. 0007 suggests that the protection circuit M110 detects the fault condition by use of the sense voltage and limiting the output current flowing through the main transistor M102].
Regarding claim 2, Kojima discloses that the protection circuit comprises:
a first transistor [Fig. 3, transistor M110], wherein the first transistor is connected between a gate electrode of the high-electron mobility transistor and a first power voltage [Fig. 3, M110 is connected between the gate of M102 and 109], and wherein a gate electrode of the first transistor is configured to receive the short-circuit protection voltage from the short-circuit detection circuit [Fig. 3, the gate of the first transistor M110 receives the sense voltage converted by sensed and converted by M103 and Rs120].
Regarding claim 11, Kojima discloses a semiconductor device comprising:
a high-electron mobility transistor [Fig. 3, M102];
a first transistor [Fig. 3, M110], wherein the first transistor is connected between a gate electrode of the high-electron mobility transistor and a second power voltage [Fig. 3, M110 is connected between the gate of M102 and ground 109], and wherein a gate electrode of the first transistor is connected to a first node [Fig. 3, gate of M110 is connected to a node between M103 and Rs120];
a second transistor [Fig. 3, M103], wherein the second transistor is connected between a drain electrode of the high-electron mobility transistor and the first node [Fig. 3, M103 is connected between/to the drain of M102 and the node as shown], wherein a gate electrode of the second transistor is connected to the gate electrode of the high-electron mobility transistor [Fig. 3, gate of M103 is connected to the gate of M102]; and
a first resistor [Fig. 3, Rs120] that is connected between the first node and the second power voltage [Fig. 3, Rs120 is connected between the node and ground 109].
Regarding claim 16, Kojima discloses a power semiconductor system comprising:
a high-electron mobility transistor [Fig. 3, M102];
a gate driver [Fig. 3, 106] configured to output a gate voltage to a gate electrode of the high-electron mobility transistor; and
a short-circuit protection device [Fig. 3, 104] connected to the gate electrode of the high-electron mobility transistor, wherein the short-circuit protection device comprises:
a short-circuit detection circuit [Fig. 3, M103, Rs120] configured to output a short-circuit protection voltage based on the gate voltage and a drain voltage of the high-electron mobility transistor; and
a protection circuit [Fig. 3, M110] configured to output a gate voltage of the high-electron mobility transistor based on the short-circuit protection voltage [par. 0007].
Regarding claim 17, Kojima discloses that the protection circuit comprises a first transistor [Fig. 3, M110], wherein the first transistor is connected between the gate electrode of the high-electron mobility transistor and the first power voltage [Fig. 3, M110 is connected between the gate of M102 and 109], and wherein a gate electrode of the first transistor is configured to receive the short-circuit protection voltage [Fig. 3, the gate of M110 is configured to receive the sense voltage from the node between M103 and Rs120].
Allowable Subject Matter
Claims 3-10, 12-15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 3: The prior art does not disclose that the short-circuit detection circuit comprises an AND gate circuit, wherein the AND gate circuit comprises a first input end for receiving the gate voltage of the high-electron mobility transistor and a second input end for receiving the drain voltage, and wherein the AND gate circuit further comprises an output end for outputting the short-circuit protection voltage. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 12: The prior art does not disclose that the semiconductor device further comprises: a third transistor, wherein the third transistor is connected between the drain electrode of the high-electron mobility transistor and the second transistor, and wherein a gate electrode the third transistor is connected to a second power voltage; and a second resistor that is connected between the third transistor and the first power voltage. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 13: The prior art does not disclose that the semiconductor device further comprises: a fourth transistor, wherein the fourth transistor is connected between the gate electrode of the high-electron mobility transistor and the gate electrode of the second transistor, and wherein a source electrode of the fourth transistor and a gate electrode of the fourth transistor are connected to each other; and a third resistor that is connected between the fourth transistor and the first power voltage.
The following is an examiner’s statement of reasons for allowance of claim 14: The prior art does not disclose that the semiconductor device further comprises: a fifth transistor, wherein the fifth transistor is connected between a second node and the first power voltage, and wherein a gate electrode of the fifth transistor is connected to the first node; a fourth resistor that is connected between the second node and the second power voltage; a sixth transistor, wherein the sixth transistor is connected between a third node and the first power voltage, and wherein a gate electrode of the sixth transistor is connected to the second node; and a fifth resistor that is connected between the third node and the second power voltage, and wherein the gate electrode of the first transistor is connected to the third node.
The following is an examiner’s statement of reasons for allowance of claim 18: The prior art does not disclose that the short-circuit detection circuit comprises an AND gate circuit, wherein the AND gate circuit comprises a first input end for receiving the gate voltage, a second input end for receiving the drain voltage, and an output end for outputting the short-circuit protection voltage, wherein the AND gate circuit is configured to output a first-level short-circuit protection voltage when the drain voltage of the high-electron mobility transistor and the gate voltage of the high-electron mobility transistor have levels higher than or equal to a reference voltage, wherein the AND gate circuit is configured to output a second-level short-circuit protection voltage when at least one of the drain voltage of the high-electron mobility transistor and the gate voltage of the high-electron mobility transistor has a lower level than the reference voltage, and wherein the first-level is equal to or greater than a threshold voltage of the first transistor, the second-level is less than a threshold voltage of the first transistor, and the second-level short-circuit protection voltage is lower than the first-level short-circuit protection voltage. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838
Prosecution Insights