DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119, which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 12-6-2024 and 1-14-2026 have been considered by the examiner (see attached PTO-1449).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 to 4, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kusko et al. (USPAP 2019/0094298).
Claim 1, 19 and 20:
Kusko substantially teaches the claimed invention. Kusko teaches a method and an apparatus for functional testing and diagnostics for integrated circuits, the apparatus comprising a test and diagnostic system (102) connected to a device under test (DUT) (112) (see fig. 1 and par. oo34). Kusko teaches that the test and diagnostic system includes a processor (104) and a memory system (106) wherein the processor executes the test and diagnostic sequencer (108) that executes one or more portions of the functional execution sequences (114) on the DUT (see par. 0035). Kusko teaches that the functional execution sequences are to verify operation of the DUT and to diagnose a cause of one or more failures (see par. 0035). Kusko teaches that a script can be used to aid in isolating the cause of a failure in combination with the DUT layout definition (see par. 0035). Kusko teaches that the failure information is captured in the test results to indicate a likely failure caused in the DUT (see par. 0035).
Kusko teaches that the DUT comprises a logic under test (120) having various logic circuits with latches and logic blocks and a memory under test (122) (“functional blocks”) wherein the functional execution sequences can include a sequence of instructions that invoke a sequence of operations on either or both of the logic under test and/or the memory under test (see par. 0037). Kusko teaches that a dynamic clock switching operation utilized by the functional execution sequences module to isolate a functional fail cycle or fail cycle range processes signal received from the DUT (see par. 0037 et sq.). Kusko fails to specifically teach the limitation of “an error separator configured to separate errors within the received pattern associated with different functional blocks of the plurality of functional blocks of the device under test during an execution of a test program;” however, this teaching is obvious to the teachings of Kusko since Kusko teaches a method for functional test and diagnostics for integrated circuits comprises identifying one or more causes of failures and isolating the one or more causes of failures by issuing one or more functional test exercisers to execute in a functional execution sequence for DUT that is selected from functional execution sequences to target a particular portion of the DUT (see par. 0079 et seq.). Kusko teaches that applying techniques for identifying cause of faults and isolates the faults for DUT increases the testing efficiency.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kusko to include the limitation of “an error separator configured to separate errors within the received pattern associated with different functional blocks on the plurality of functional blocks of the device under test during an execution of a test program” because Kusko teaches that a method and an apparatus for functional test and diagnostics of integrated circuits comprises efficiency testing of DUT’s by identifying the causes of the faults and isolating the faults. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for efficiency testing of DUT’s using a fault isolation technique as taught by Kusko (see par. 0092).
As per claims 2 and 3, Kusko teaches that a dynamic (“on-the-fly”) clock switching operation utilized by the functional execution sequences module to isolate a functional fail cycle or fail cycle range processes signal received from the DUT (see par. 0037 et sq.). Kusko teaches that based on structural DFT (design for test), a dynamic clock switching may be used to identify and isolate fails (see par. 0038).
As per claim 4, Kusko teaches that the memory system of the test and diagnostic system comprises afunctional execution sequences that may be a device for implementing the functions (see par. 0101).
Allowable Subject Matter
Claims 5 to 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Frediani et al. (YSPAP 2014/0236524) discloses automated test equipment capable of performing a high-speed test of semiconductor devices.
Yang (USPAP 2014/0157067) discloses a method and an apparatus for applying at-speed functional test.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/Primary Examiner, Art Unit 2112