CTNF 18/972,272 CTNF 84811 Detailed Action 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This is in response to Application with case number 18/972,272, filed on 12/06/2024 in which claims 1-20 are presented for examination. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-20 are pending, of which claims 1, 11 and 16 are in independent form. Specification The examiner notes that the Specification does not include any URL links and Trademark terms requiring capitalization. The examiner notes that the abstract is in narrative form and is limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. In addition, the examiner notes that the abstract is not using legal phraseology often used in patent claims. IDS References cited in the IDS filed on 12/6/2024 have been considered by the examiner. Priority Applicant’s claim of benefit of priority based on US Provisional Application 63/044,741 filed on 6/26/2020 is acknowledged by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.jsp. Claims 1-20 of the instant application are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over the claims 1- 20 of US Patent No. 12,184,795 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter of the instant application would have been obvious to one of ordinary skill in the art in light of the disclosure of each application or patent listed above and because both applications disclose system and method for physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device and using indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit, each indirection process identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address and applying hashing to the hidden content stored by the OTP memory device to generate the key. Claim limitations of claims 1 and 6 of US Patent No. 12,184,795 anticipates all the limitations of claim 1. Claim 2 of instant application includes similar limitations as those of claim 2 of US Patent No. 12,184,795. Claim limitations of claim 1 of US Patent No. 12,184,795 anticipates all the limitations of claims 3 and 7. Claim 4 of instant application includes similar limitations as those of claim 3 of US Patent No. 12,184,795. Claim 5 of instant application includes similar limitations as those of claim 4 of US Patent No. 12,184,795. Claim 6 of instant application includes similar limitations as those of claim 5 of US Patent No. 12,184,795. Claim 8 of instant application includes similar limitations as those of claim 7 of US Patent No. 12,184,795. Claim 9 of instant application includes similar limitations as those of claim 9 of US Patent No. 12,184,795. Claim 10 of instant application includes similar limitations as those of claim 10 of US Patent No. 12,184,795. Claim limitations of claims 12 and 16 of US Patent No. 12,184,795 anticipates all the limitations of claim 11. Claim 12 of instant application includes similar limitations as those of claim 12 of US Patent No. 12,184,795. Claim 13 of instant application includes similar limitations as those of claim 13 of US Patent No. 12,184,795. Claim 14 of instant application includes similar limitations as those of claim 14 of US Patent No. 12,184,795. Claim 15 of instant application includes similar limitations as those of claim 15 of US Patent No. 12,184,795. Claim 16 of instant application includes similar limitations as those of claim 17 of US Patent No. 12,184,795. Claim limitations of claim 18 of US Patent No. 12,184,795 anticipates all the limitations of claim 17. Claim 18 of instant application includes similar limitations as those of claim 18 of US Patent No. 12,184,795. Claim 19 of instant application includes similar limitations as those of claim 19 of US Patent No. 12,184,795. Claim 20 of instant application includes similar limitations as those of claim 9 of US Patent No. 12,184,795. Relevant Prior Arts : Tuyls et al. (US 2019/0147967 A1) teaches a programming device arranged to obtain and store a random bit string in a memory device, the memory device comprising multiple one-time programmable memory cells, a memory cell having a programmed state and a not-programmed state, the memory cell being one-time programmable by changing the state from the not-programmed state to the programmed state through application of an electric programming energy to the memory cell. Garner et al. (US 2009/0327709 A1) teaches provide, to a memory device, an obfuscated clear-page address derived from a clear-page address that is not the same as a key-page address and/or providing, to the memory device, an obfuscated key-page address derived from the key-page address when the obfuscated clear-page address is the same as the key-page address. Royer et al. (US 2017/0160987 A1) teaches a memory system with main memory where the main memory includes first level main memory and second level main memory, the first level main memory configured to store indirection information providing reference to physical memory units of the second level main memory . Further, the memory system includes a memory controller configured to initiate an access of a physical memory unit of the second level main memory using the indirection information stored in the first level main memory. Rigoni et al. (US 2021/0294694 A1) teaches retrieving a first encoded data packet from a first address in the non-volatile storage device; decoding the first encoded data packet to obtain a first data item and a first error code corresponding to the first data item, the first encoded data packet being decoded by using a first coding key that is associated with the first address; detecting whether the first data item is corrupt based on the first error code and an error correction function, storing the first data item at a first address in the volatile storage device when the first data item is not corrupt, and transitioning the electronic device into a safe state when the first data item is corrupt. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tuyls et al. (US 2019/0147967 A1) hereinafter Tuyls in view of Rigoni et al. (US 2021/0294694 A1) hereinafter Rigoni . Tuyls teaches a method comprising: receiving, by a controller ( e.g., integrated circuit 120 ), a set of input bits (see para. [0021] “In one approach, the device 110 transmits a set of input bits 115 to the integrated circuit 120 through the communication link to access content stored by the integrated circuit 120. The integrated circuit 120 may receive the set of input bits 115.”) ; obtaining, by the controller, an input address by converting a portion of the set of input bits [according to a hash function] (see para. [0030] “…the address generator 232 applies the first portion of the set of input bits to a hash function to generate the input address 240. The address generator 232 may shift the first portion … and apply the shifted portion to the hash function. An example hash function includes an XOR operation …”) ; applying, by the controller, the input address to a first memory device (see pars. [0028]-[0029] “in some embodiments, the content processor 230 is a component that applies an address 240 to the OTP memory device 135 and obtains hidden content 245 from the OTP memory device 135 through indirection processes.”; see para.[0030] “The address generator 232 may apply the input address 240 to the OTP memory device 135.”; see para. [0036] “The 5 bit address 240 may be applied to the OTP memory device 135 to obtain subsequent content 245.”) ; generating, by the controller, a key based on hidden content stored by the first memory device according to the input address applied (see para. [0033] “In one aspect, the key generator 270 is a component that receives the hidden content and generates the key 125 according to the hidden content received. In one aspect, the key generator 270 generates the key 125 by applying the hidden content to a hash function.”; see para. [0053]-[0054] “in one approach, the PUF controller 140 generates the key 125 according to the hidden content 245. For example, the PUF controller 140 may apply the hidden content to a hash function to generate the key 125 …”) ; and accessing content stored by a second memory device based on the key (see pars. [0021]-[0022] “In some embodiments, the SRAM 160 may store data or content. … The SRAM 160 may be enabled or accessed, in response to a valid key 125 . The PUF device 130 may receive the set of input bits 115 from the device 110 and generate a key 125 according to the set of input bits 115. The PUF device 130 may transmit the key 125 to the SRAM 160 to enable access to the content stored by the SRAM 160 … the generated key 125 is used to enable access to content stored in a second memory (SRAM 160)”). Tuyls discloses converting a portion of the received input bits into an input address by applying hash function (i.e., XOR + shift) and describes hashing a portion of input bits to produce an input address (see par. 30) but fails to explicitly teach obtaining… according to a hash function. Rigoni explicitly teaches obtaining, by the controller, an input address by converting a portion of the set of input bits according to a hash function (see para. [0041] “When a data item is stored at a given address in the non-volatile storage device, an error code for the data item is generated. The error code is added to the data item to produce a data packet. … The data packet is encoded with a given coding key that is associated with the given address and the encoded data packet may be stored at the given address.”; see para. [0042] “In some implementations, at least some of the addresses in the non-volatile storage device 102 may be associated with different hashing vectors.”; see para. [0035]-[0036] “Figs 5-8 is a plot of a one-to-one mapping function 500, which maps each of the addresses in an address space of the non-volatile storage device 102 to a different hashing vector. … the mapping function 500 maps each of a plurality of hashing vectors to a different one of the addresses in the address space … such that only one address is mapped to any of the hashing vectors.” … teachings of mapping an address to an address-specific hashing/coding vector via an explicit mapping function …Rigoni provides an explicit address hash/vector mapping function (see pars. 35-36 &42) and address-based encoding/decoding). Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the application to implement Rigoni’s address hash/vector mapping at the address generation or read stage taught in Tuyls to hide OTP addressing and detect address errors, a predictable design choice using well-known primitives (XOR, table lookups) to achieve enhanced security and safety (see Rigoni, pars. 36 and 41-43). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEE K SONG whose telephone number is (571)270-3260. The examiner can normally be reached on M-F 9:00 am – 5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eleni Shiferaw can be reached on (571)272-3867 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-7291. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HEE K SONG/PRIMARY Examiner, Art Unit 2497 Application/Control Number: 18/972,272 Page 2 Art Unit: 2497 Application/Control Number: 18/972,272 Page 3 Art Unit: 2497 Application/Control Number: 18/972,272 Page 4 Art Unit: 2497 Application/Control Number: 18/972,272 Page 5 Art Unit: 2497 Application/Control Number: 18/972,272 Page 6 Art Unit: 2497 Application/Control Number: 18/972,272 Page 7 Art Unit: 2497 Application/Control Number: 18/972,272 Page 8 Art Unit: 2497 Application/Control Number: 18/972,272 Page 9 Art Unit: 2497 Application/Control Number: 18/972,272 Page 10 Art Unit: 2497 Application/Control Number: 18/972,272 Page 11 Art Unit: 2497 Application/Control Number: 18/972,272 Page 12 Art Unit: 2497
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